This document provides an overview of the ARM Cortex-M3 subsystem and its peripherals. It discusses the Cortex-M3 processor core and its features like the pipeline, instruction set, registers and exception handling. It also describes the peripherals like DMA, UART, timers and watchdog. The document outlines the development tools like uVision IDE and debugger. It discusses the software development flow including building, downloading and debugging programs on the target board.

1. ARM Training
CortexM3 Subsystem
Date – 28/03/2012
raghav.nayak@st.com

2. 2
Agenda
 CortexM3 Subsystem
 Peripherals
 SW Development
 Debugging
 Tool Demo

3. CortexM3 Processor
 CortexM3 Core
 Nested Vector Interrupt Controller
 Bus Interface
 Debug Access Port
 Memory Protection Unit
 ETM, ITM and TPIU
 WIC
 Flash Patch Breakpoint
 Data Watchpoint and Trace
 ROM Table
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4. Garnet Implementation
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5. 5
CortexM3 Core
 ARM v7M Architecture
 Harvard Architecture
 3 stage pipeline
 Thumb and Thumb-2
Instruction set
 Low latency interrupt
handling
 Speculative Branch
Prediction
 Single cycle multiplication
 H/W division support
 Unaligned access
 Big Endian support

6. Modes and States
 Execution State
 Thumb
 Debug
 Execution Mode
 Thread
 Handler
 Resource Access
 Privileged
 User or Unprivileged
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7. Data Types and Registers
 Data Type Support
 Byte, Half-Word and Word
 32 bit pointer
 Signed or unsigned Byte, Half-Word, Word and
Double word
 Registers
 16 32-bit register
 R0-R12 general purpose register, SP, LR and PC
 Banked Stack Pointer (Main and Process)
 3 Program Status Register
 3 Mask Register
 1 Control Register – 3 bit to select access/stack
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8. Registers …cont…
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9. Registers …cont…
 Program Status Register (PSR)
 Application PSR
 N, C, Z, V, Q and GE[3-0] Condition flags
 Interrupt PSR
 Holds the exception number of the currently executed
exception
 Execution PSR
 T and ICI/IT bit fields
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10. Registers …cont…
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 Mask Register
 PRIMASK
 1-bit Register
 changes the execution priority to 0(Highest Priority)
 FAULTMASK
 1-bit Register
 Changes the execution priority to -1(Hard Fault)
 BASEPRI
 8-bit Register
 Changes the priority level required for preemption

11. Instruction Set
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 Unified Assembly Language Syntax
 16 bit or 32 bit Instructions
 Data Processing
 MOV, ASR, LSL, ROR, ADD, SUB, REV, MUL, UDIV, CMP,
TST, CMN, AND, ORR, BIC, BFI, EOR, CPY
 Process control
 B, BX, BL, CBNZ, CBZ
 Load/Store
 LDR, STR, LDRH, STRH, LDRB, STRB, LDRD, STRD, LDM,
STM, LDREX, STREX
 Serial/Miscellaneous
 DMB, DSB, ISB, WFI, WFE, MRS, MSR, CPS, SEV, CLREX,
SVC

12. Exception
 Synchronous or Asynchronous events
 External or System events
 Reset, Supervisor Call, Fault or Interrupt
 Preempting exception
 Active, Pending, Active-Pending or Inactive state
 Programmable priority
 Except Reset = -3, NMI = -2 and HardFault = -1
 Stack context supports AAPCS
 Exception handler should be AAPCS compliant
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13. Exception …cont…
 Entry Behavior
 Stack Alignment correction
 Hardware saves context state to stack
 Exit Behavior
 POP/LDM, LDR or BX loads 0xFxxxxxxx into PC
 Hardware restores context state from stack
 Revert Stack alignment correction
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14. Exception …cont…
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 Vector is fetched in parallel to stack activity
 R0-R3, R12, xPSR, LR and PC stored and
restored by hardware
 12 cycle latency PUSH/POP

15. Exception …cont…
 Tail Chaining Exception
 Optimized exception entry and exit sequence
 Six clock cycle for zero wait state memory
 No stack PUSH and POP operation
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16. Exception …cont…
 Late arriving exception
 High priority exception handling during exception entry
sequence
 Optimized exception entry and exit sequence
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17. Fault
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 MemManage
 Generated by MPU
 instruction or data memory access
 BusFault
 Memory access failures due to error in Bus Activity
 Instruction and data transaction
 HardFault
 Generic fault used for escalation
 UsageFault
 Non-memory related events caused by instruction
 Undefined instruction, invalid state, exception return

18. Bit Banding
 enable direct access to single bit of data
 32MB alias region mapped to 1MB bit band
region
 Memory access is atomic
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19. Nested Vector Interrupt Controller
 32 external interrupts and 5-bit priority level
 Reduced interrupt latency
 Supports nesting interrupt
 Supports dynamic priority
 Controls power management scheme
 Supports both level and edge triggered interrupt
 Privileged access
 Little endian register access
 Supports Non Maskable Interrupt (NMI)
 Provides 24-bit down timer (SysTick)
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20. Bus Interface
 32-bit AMBA3 AHB Lite Port
 ICode Interface
 Instruction fetch from memory range 0x0-0x1FFFFFFF
 No debug access
 DCode Interface
 Data and debug access on memory range 0x0-0x1FFFFFFF
 System Interface
 Instruction, Data and debug access on memory range
0x20000000-0xDFFFFFFF and 0xE0100000-0xFFFFFFFF
 32-bit AMBA3 APB port
 Private Peripheral Bus
 Data and debug access on memory range 0xE0000000-
0xE00FFFFF
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21. System Memory Map
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22. System Control Space
 32 bit registers in 4KB address space
 CPUID and vendor Identification
 Fault detection and handling
 Interrupt configuration, detection and handling
 Exception priority control
 Sleep Mode handling
 Debug control and status
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23. Debug
 Invasive debug
 2 hardware and 6 software breakpoint
 Based on CoreSight debug architecture
 Serial Wire and JTAG Debug Port
 FPB supports halt, single step execution
 AHB-AP provides access to memory and
registers in the system
 Target Identification
 Read the CPUID register from System Control Space
in ROM table
 Breakpoint information from FPB in ROM table
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24. Peripherals
 DMA
 8 channels, 16 requests through 16 line
 2 Master and 1 Slave port
 2 interrupt request line
 Single and Burst request with burst length 1024 bytes
 Flow control and big endian support
 UART
 Max 460800 and Min 110 baud
 Programmable baud rate, stop bit, parity bit, FIFO
trigger level, flow control
 32X8 transmit and 32X12 receive FIFO
 DMA and Interrupt support
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25. Peripherals …cont…
 Dual Timer
 2 configurable 32 or 16 bit down counters
 Free running, periodic or one-shot
 Programmable 1, 16 or 256 pre-scalar values
 Runs at Core clock
 interrupt signaling on zero count
 Watchdog
 32 bit down counter
 Enabled or disabled by software
 Reset the system to recover from software failure
 Provides mechanism to avoid unauthorise access
 Runs at Core clock
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26. MDK-ARM Tool
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27. uVision4 IDE
 Source code editor
 Device database
 Project Manager
 Integrated Make utility
 Dialogs for
Environment Setting
 Target CPU Simulator
 Flash Program Utility
 Debug using ULINK
Debug Adapter
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28. Software Development Cycle
 Create a new Project
 Configure device database and tool setting
 Create new source files and add to the project
 Build the project
 Fix build errors
 Optimize application
 Download image to Flash ROM or SRAM
 Execute the application
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29. ULINK2 Pro
 Provides interfaces
 JTAG to target board
 USB to Host PC
 Supports
 Checking memory and
registers
 Breakpoints and single
step execution
 Image download and
execution in real-time
 Program memory flash
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30. Coding Hint
 Speed optimization
 Size optimization
 Power optimization
 MicroLIB to reduce code size
 Use 32 bit variables for local and parameters
 Place scalars at the beginning of a struct variable
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31. Startup code
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32. Startup code ..cont…
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33. Scatter file
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34. Build Mode
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35. Debug Mode
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36. IP Validation
 Stand alone validation
 Independent of OS
 Independent of Flash/ROM code
 CPU Startup and Interrupt Initialization code
 Scatter file for flexible code execution
 No additional latency due to OS
 Single test or All test execution
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37. Questions?
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38. Reference
 Garnet Architecture specification
 ARMv7-M architecture reference manual
 CortexM3 Technical reference manual
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10.201.59.94specs