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ARM Architecture for Kernel Development
The document discusses ARM architecture focusing on kernel development, highlighting ARM's RISC design and separate instruction/data pathways. It covers registers, exception handling, memory management units (MMUs), and instruction specifics for both ARMv7 and ARMv8 architectures. Additionally, it includes references to ARM architecture manuals and provides contact information for further inquiries.
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ARM Architecture for Kernel Development
- 1. 1 Embedded TechTalk #2: ARMArchitecture for Kernel Development Andrew Lukin 2017-08-10
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- 3. 3 RISC -- ReducedInstructions Set Computer ● Small set of simple and general instructions ● Fixed length instructions ● Simpler processor’s core logic ● Harvard architecture -- architecture with physically separate storage and signal pathways for instructions and data ● Load/Store architecture -- separate instructions for memory access ● A lot of general purpose registers or even register files
- 4. 4 Evolution of theARM architecture
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- 12. 12 Exceptions ● A synchronousexception if it is generated as a result of execution or attempted execution of the instruction stream, and where the return address provides details of the instruction that caused it. ● An asynchronous exception is not generated by executing instructions, while the return address might not always provide details of what caused the exception. ● In the ARMv7-A architecture, the prefetch abort, Data Abort and undef exceptions are separate items. ● In AArch64, all of these events generate a Synchronous abort. The exception handler may then read the syndrome and FAR registers to obtain the necessary information to distinguish between them.
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- 15. 15 Execution states -Registers mapping
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- 19. 19 MMU - Caches ●Point of Coherency (PoC) -- is the point at which all observers, for example, cores, DSPs, or DMA engines, that can access memory, are guaranteed to see the same copy of a memory location. Typically, this is the main external system memory. ● Point of Unification (PoU) -- is the point at which the instruction and data caches and translation table walks of the core are guaranteed to see the same copy of a memory location
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- 21. 21 MMU - Normalmemory ● Normal memory -- The processor can re-order, repeat, and merge accesses to it. Furthermore, address locations that are marked as Normal can be accessed speculatively by the processor, so that data or instructions can be read from memory without being explicitly referenced in the program, or in advance of the actual execution of an explicit reference. Such speculative accesses can occur as a result of branch prediction, speculative cache linefills, out-of-order data loads, or other hardware optimizations.
- 22. 22 MMU - Devicememory ● Device memory -- ○ Device-nGnRnE most restrictive (equivalent to Strongly Ordered memory in the ARMv7 architecture). ○ Device-nGnRE ○ Device-nGRE ○ Device-GRE least restrictive ● Gathering of non Gathering (G or nG) -- whether multiple accesses can be merged into a single bus transaction for this memory region. ● Re-ordering (R or nR) -- whether accesses to the same device can be re- ordered with respect to each other. ● Early Write Acknowledgement (E or nE) -- whether an intermediate write buffer between the processor and the slave device being accessed is allowed to send an acknowledgement of a write completion
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- 27. 27 Multiplication instructions inassembly language
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- 31. 31 Links 1. Programmer’s Guidefor ARMv8-A (DEN0024A) 2. ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile DDI0487B_a_armv8.pdf 3. ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition DDI0406C_C_arm_architecture_reference_manual.pdf
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- 33. 33 Thank you Andrew Lukin SrEmbedded Developer andrii.lukin@globallogic.com +380-95-303-43-76