2. EMBEDDED SYSTEMS
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COURSE OBJECTIVES:
To study the architecture of LPC 2148 ARM
processor.
To learn the design aspects of LPC 2148’s i/o and
memory interfacing circuits.
To study about communication and bus interfacing.
COURSE OUTCOMES:
Design and implement programs on LPC 2148 Arm
processor.
Design various scheduling algorithms.
Work with Task and Time management functions.
3. Syllabus
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MODULE I
ARM INTRODUCTION
Introduction - The ARM Architecture Overview - Instruction set Summary - Processor
operating states- Memory formats - Memory Interface - Bus interface signals -
Addressing signals Addressing timing - Data Timed Signals - Debug interface - Debug
systems - Debug interface signals - ARM7TDMI Core and system state - About
Embedded ICE-RT Logic – Instruction Set.
MODULE II
LPC2148 ARM CPU
Introduction: - Architectural Overview - Memory Mapping -Block Diagram System control
block functions: PLL - Power Control - Reset - VPB Divider - Wakeup Timer - Memory
Acceleration Module - Timer0 and Timer1- PWM - RTC - On Chip ADC - On Chip
DAC- Interrupts- Vector Interrupt Controller.
MODULE III
LPC 2148 – PERIPHERALS
General Purpose Input/Output Ports (GPIO) - Universal Asynchronous
Receiver/Trasmitter
(UART) - I2C Interface – Multimaster and Multislave communication - SPI Interface - SSP
Controller – USB 2.0 Device Controller.
4. Syllabus
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MODULE IV
OPERATING SYSTEM OVERVIEW
Introduction OS – Function of OS – Defining an RTOS – Differences in
Embedded Operating Systems – Introduction to Kernel – Resources
– Shared Resources - Defining a Task – Task States - Multitasking -
Scheduling and Scheduling Algorithms - Context Switching – Clock
Tick – Timing of Task.
MODULE V
ΜC/OS – II
Introduction–II Task Management Functions – Creating a Task - Time
Management Functions – OS Delay Functions - Implementation of
Scheduling and rescheduling.
LEARNING RESOURCES:
5. Syllabus
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Text Books:
Embedded Systems Architecture - Tammy Noergaard, Newnes 2005.
ARM System Developer‟s Guide – Andrew N.Sloss.
ARM Architecture Reference Manual - David Seal.
ARM System-on-Chip Architecture (2nd Edition) by Steve Furbe.
References:
Micro C/OS – II The Real Time Kernel Jean J. Labrosse.
Real Time Concepts for Embedded Systems – by Qing Li and Caroline Yao,
2003
Embedded / Real Time Systems : Concepts , Design & Programming by Dr.
K.V.K.K PRASAD.
LPC 2148 User Manual.
6. ARM7TDMI Architecture
The ARM7TDMI is a member of the Advanced RISC
Machines (ARM) family of general purpose 32-bit
microprocessors, which offer high performance for very
low power consumption and price.
Advanced RISC machine (ARM) is the first reduced
instruction set computer (RISC) processor for commercial
use, which is currently being developed by ARM Holdings
These processors are specifically used in portable
devices like digital cameras, mobile phones, home
networking modules and wireless communication
technologies and other embedded systems
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9. Arithmetic Logic Unit (ALU)
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The ALU has two 32-bits inputs. The primary comes
from the register file, whereas the other comes from
the shifter. Status registers flags modified by the ALU
outputs. The V-bit output goes to the V flag as well
as the Count goes to the C flag.
Whereas the foremost significant bit
really represents the
S flag, the ALU output operation is done by
NORed to get the Z flag.
The ALU has a 4-bit function bus that permits up to
16 opcode to be implemented.
10. BOOTH Multplier
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The multiplier factor has 3 32-bit inputs and the
inputs return from the register file. The multiplier
output is barely 32-Least Significant Bits
Booth algorithm is a noteworthy multiplication
algorithmic rule for 2’s complement numbers. This
treats positive and negative numbers uniformly.
11. Barrel Shifter
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The barrel shifter features a 32-bit input to be
shifted. This input is coming back from the register
file or it might be immediate data.
The shifter has different control inputs coming back
from the instruction register.
The Shift field within the instruction controls the
operation of the barrel shifter.
This field indicates the
kind of shift to be performed (logical left or right
, arithmetic right or rotate right).
12. Control Unit
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For any microprocessor, control unit is the heart of
the whole process and it is responsible for the
system operation.
The control unit is sometimes a pure combinational
circuit design. Here, the control unit is implemented
by easy state machine.
The processor timing is additionally included within
the control unit.
Signals from the control unit are connected to each
component within the processor to supervise its
operation.
13. ARM Features
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• 32-bit RISC-processor core (32-bit instructions)
• 37 pieces of 32-bit integer registers (16 available)
• Thumb instruction set
• Pipelined (ARM7: 3 stages)
• Cached (depending on the implementation)
•Von Neuman-type bus structure (ARM7), Harvard (ARM9)
• Debug Interface
• Embedded ICE macrocell
• Jazelle DBX(Direct Bytecode eXecution)
• 8 / 16 / 32 -bit data types
• 7 modes of operation (usr, fiq, irq, svc, abt, sys, und)
• Simple structure -> reasonably good speed / power
consumption ratio
14. THUMB set
The THUMB set’s 16-bit instruction length allows it to
approach twice the density of standard ARM code
while retaining most of the ARM’s performance
advantage over traditional 16-bit processor using 16-
bit registers.
This is possible because THUMB code operates on
the same 32-bit register set as ARM code.
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15. THUMB set
The key idea behind THUMB is that of a super-
reduced instruction set.
EssentiallyARM7TDMI processor has two instruction
sets:
the standard 32-bit ARM set
a 16-bit THUMB set
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16. THUMB set
THUMB code is able to provide up to 65% of the
code size of ARM
And 160% of the performance of an equivalent ARM
processor connected to a 16-bit memory system.
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17. pipelining
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It is used speed up the no. of execution per unit
time for processor by instruction parallelism
The process of fetching the next instruction when
the present instruction is being executed is called
as pipelining
Pipelining is a technique that implements a form of
parallelism called instruction-level parallelism within
a single processor.
It therefore allows faster CPU throughput (the
number of instructions that can be executed in a unit
of time) than would otherwise be possible at a given
clock rate.
18. Instruction execution without pipeline
The execution of instruction performed one by one,
after complete the execution of an instruction the next
instruction is fetched from the memory
Suppose, these instructions are executed
sequentially, and it takes the 1-unit clock cycle for each step
to run. So, it would take 12-clock cycles(3 X 4) to execute
these instructions.
19. 3 StagePipeline
The pipeline is used to overcome the delay caused by instruction fetching
and decoding before execution.
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20. 3 StagePipeline
Fetch
– The instruction is fetched from memory and placed in the
instruction pipeline
Decode
– The instruction is decoded and the data path control signals prepared
for the next
cycle
Execute
– The register bank is read, an operand shifted, the ALU result
generated and
written back into destination register
The three stage pipeline has hardware independent stages that
execute one instruction while decoding a second and fetching a
third.
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21. Cache
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Cache is a small amount of memory which is a part
of the CPU - closer to the CPU than RAM . It is used
to temporarily hold instructions and data that the
CPU is likely to reuse.
ARM3 has an on chip cache of 4kB
ARM3 has an on chip cache of 8kB
22. Harvard architecture vs Von-Neumann
architecture
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In Harvard architecture, the CPU is connected with
both the data memory (RAM) and program memory
(ROM), separately.
In Von-Neumann architecture, there is no separate
data and program memory. Instead, a single
memory connection is given to the CPU.
24. Debug Interface
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On chip unit for testing called as JTAG interface
JTAG stands for Joint Test Action Group and defines
the set of standards for testing the functionality of
hardware.
There is a set of scan cells located at the boundaries
26. Embedded ICE macrocell
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Macro cell ICE(In Circuit Emulator) is used to enable
the testing .
This unit is powered by breakpoint and watch point
register and control & status register
All the register work together to halt the ARM core to
read status and thus do active debugging
27. Jazelle DBX(Direct Bytecode eXecution)
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ARM processors to execute Java byte code in
hardware as a third execution state along with
existing ARM and Thumb mode
Useful to increase the execution speed of Java ME
games and applications
28. Operating Modes
ARM has seven operating modes:
User : Unprivileged mode under which most tasks run
FIQ(Fast Interrupt Request ): Entered on a high priority
interrupt request
IRQ(Interrupt Request): Entered on a low priority request
Supervisor: Entered on reset and when a software
interrupt instruction is executed.
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29. Abort: used to handle memory access violations
Undef: used to handle undefined instructions
System: privileged mode using the same register as user
mode
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31. Processor Operating States
The ARM7TDMI can be in one of two states:
ARM state
which executes 32-bit, word-aligned ARM instructions.
THUMB state
which operates with 16-bit, halfword-aligned THUMB
instructions. In this state, the PC uses bit 1 to select between
alternate halfwords.
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32. Switching State
Entry into THUMB state
it can be achieved by executing a BX instruction with the
state bit (bit 0) set in the operand register.
Transition to THUMB state will also occur automatically on
return from an exception(IRQ, FIQ, UNDEF, ABORT, SWI
etc.), if the exception was entered with the processor in
THUMB state.
Entry into ARM state happens:
On execution of the BX instruction with the state bit clear
in the operand register.
On the processor taking an exception (IRQ, FIQ,
RESET, UNDEF, ABORT, SWI etc.)
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33. Memory Formats
ARM7TDMI views memory as a linear collection of bytes numbered
upwards from zero.
Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second and
so on.
Types
Big Endian format.
Little Endian format.
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34. Big endian format
In Big Endian format, the most significant byte of a word is stored at
the lowest numbered byte and the least significant byte at the highest
numbered byte.
Byte 0 of the memory system is therefore connected to data lines 31
through 24.
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35. Little endian format
In Little Endian format, the lowest numbered byte
in a word is considered the word’s least
significant byte, and the highest numbered byte
the most significant.
Byte 0 of the memory system is therefore
connected to data lines 7 through 0.
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36. Instruction Set
Features:
Load/Store architecture
3-address data processing instructions
Conditional execution
Load/Store multiple registers
Shift & ALU operation in single clock cycle
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37. Conditional execution:
Each data processing instruction
prefixed by condition code
Result – smooth flow of instructions through pipeline
16 condition codes:
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38. brazil@20
EQ equal
MInegative
HI unsigned higher
GT signed greater than
NE not equal
PL positive or zero
LS unsigned lower or same
LE signed less than or equal
CS unsigned higher or same
VS overflow
GE signed greater than or equal
AL always
CC unsigned lower
VC no overflow
LTsigned less than
NV special purpose
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39. Types
ARM instruction set
Data processing
instructions
Data transfer
instructions
Software interrupt
instructions
Block transfer
instructions
Multiply instructions
Branching instructions
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40. Data Processing Instructions
Arithmetic and logical operations
3-address format:
Two 32-bit operands
(op1 is register, op2 is register or immediate)
32-bit result placed in a register
Barrel shifter for op2 allows full 32-bit shift
within instruction cycle
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43. Data Transfer Instructions
Load/store instructions
Used to move signed and unsigned
Word, Half Word and Byte to and from registers
Can be used to load PC
(if target address is beyond branch instruction range)
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44. Arithmetic operations:
ADD, ADDC, SUB, SUBC, RSB, RSC
Bit-wise logical operations:
AND, EOR, ORR, BIC
Register movement operations:
MOV, MVN
Comparison operations:
TST, TEQ, CMP, CMN
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45. LDR Load Word
STR Store Word
LDRH Load Half Word
STRH Store Half Word
LDRSH Load Signed Half Word
STRSH Store Signed Half Word
LDRB Load Byte
STRB Store Byte
LDRSB Load Signed Byte
STRSB Store Signed Byte
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46. Block Transfer Instructions
Load/Store Multiple instructions (LDM/STM)
Whole register ban or a subset copied to memory
or restored with single instruction
R0
R1
R2
R14
R15
Mi
Mi+1
Mi+2
Mi+14
Mi+15
LDM
STM
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47. Branch instructions
B Basic branch instruction used to jump forward or
backward of up to 32 MB.
BL Branch and Link instruction jumps to the destination and
stores a return
address in R14 (Link Register).
BX, BLX Branch, Brach Link and Exchange.
This swaps the instruction sets from ARM to THUMB
and vice versa
while jumping.
BXJ Branch and change to Jazelle state.
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48. Memory Interface
The ARM processor has Von Neumann Architecture,
with 32 bit data bus carrying both instruction and
data
Only the load, store, swap instructions can access
from the memory
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49. BUS Interface signal
ARM bus signal can be grouped as four categories
Clocking and clocking control signal
Address class signal
Memory request signal
Data timed signal
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50. Clocking and clock control
MCLK
nWAIT
ECLK
nRESET
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70. In the DRAM Based systems, When APE is high ARM processor address is valid after the
rising edge of MCLK before the memory cycle to which it refers.
This timing allows longer periods for address decoding and the generation of DRAM control
signal
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Address Class Signals
71. In the SRAM or ROM Based systems, When APE is low ARM processor
address is valid after the falling edge of MCLK before the memory cycle
to which it refers.
This timing allows longer periods for address decoding and the
generation of DRAM control signal
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72. Data timed signal
D[31:0], DOUT[31:0], DIN[31:0]
ABORT
Byte latch enable
Byte and halfword access
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74. Unidirectional data bus
When BUSEN is high, all the instructions and input data are presented on the input data bus
DIN[31:0]. Data must be setup and held to the falling edge of MCLK
all output data is presented on DOUT[31:0].
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75. Bidirectional data bus
When BUSEN is low, DIN[31:0]. DOUT[31:0] are disabled. Data must be setup and held to the
falling edge of MCLK
the signal nRW is driven HIGH to indicate a write cycle.
nENOUT is driven low to indicate that the processor is driving D[31:0]
as an output.
DATA WRITE bus cycle
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80. Debug Interface
The debug interface is based on IEEE Std. 1149.1-
1990, Standard Test Access Port and Boundary
Scan Architecture.
The ARM7TDMI processor contains hardware
extensions for advanced debugging features
These make is easier to develop application
software, operating systems and hardware itself.
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81. Stages of Debug
A request on one of the external debug signal, or on
an internal functional unit known as EmbeddedICE
Logic forces into debug state
A break point, an instruction fetch
A watch point, a data access
An external debug request
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83. Debug Host
The Debug host is computer that is running a
software debugger such as the Arm Debugger for
Windows.
The debug host allows to issue high level commands
such as setting breakpoints of examining the
contents of memory
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84. Protocol Converter
The protocol converter communicates with high
commands issued by the debug host and the low
level commands of JTAG interface.
It interfaces to the host through an interface such as
an enhanced parallel port.
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86. The EmbeddedICE Logic
This is a set of registers and comparators used to
generate debug exceptions such as breakpoints
The TAP Controller
This controls the action of the scan chains using a JTAG
serial interface
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87. Debug interface signal
There are three primary external signals associated
with the debug interface:
DBGACK
Debug acknowledge. When HIGH indicates ARM is in debug state.
DBGEN
Debug Enable.
This input signal allows the debug features of ARM7TDMI to be disabled. This
signal should be driven LOW when debugging is not required.
DBGRQ
Debug request.
IC This is a level-sensitive input, which when HIGH causes ARM7TDMI to enter
debug state after executing the current instruction.
This allows external hardware to force ARM7TDMI into the debug state, in
addition to the debugging features provided by the ICEBreaker block.
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88. ARMv7TDMI
ARM7TDMI is a core processor module embedded
in many ARM7 microprocessors,
T: capable of executing Thumb instruction set
D: Featuring with IEEE Std. 1149.1 JTAG boundary-
scan debugging interface.
M: Featuring with a Multiplier-And-Accumulate
(MAC) unit for DSP applications.
I: Featuring with the support of embedded In-Circuit
Emulator
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