Instruction selection in LLVM maps the compiler intermediate representation (IR) to target instructions by matching nodes in a selection DAG. It performs this mapping greedily by choosing instructions with higher complexity that can cover more operations. The selection DAG is legalized to ensure operations are supported by the target before instruction matching using patterns defined in tablegen files.

1. LLVM Instruction Selection

2. Instruction Selection
• What is instruction selection ?
– To match the Compiler IR (intermediate
representation) to Target instruction.

3. Instruction Selection
• Why need Compiler IR ?
– In the beginning, compiler developer use “macro
expansion”
• Directly mapping high level language to assembly code
Disadvantage: Tightly coupling the code generator to a particular programming
language.
Create Machine independent IR to isolate backend and programming language
detail.

4. LLVM retargetablity design
LLVM IR come from frontend (clang/llvm-gcc/GHC)

5. LLVM Optimization Pass
LLVM IR Pass
LLVM DAG Pass
Emit target assembly code
Instruction Selection
Flags to dump pass sequence:
clang -mllvm -debug-pass=Structure {input}.c
Target Independent Passes
Target Dependent Passes
Flags to dump optimization detail for each pass:
clang -mllvm -debug -mllvm -print-after-all {input}.c

6. What is SelectionDAG ?
• LLVM IR will transfer to SelectionDag before
Instruction Selection
• a Directed-Acyclic-Graph to present
operations
– Node present operation (E.g. add/sub/or)
– Edge present define/use relationship
t15 hi20(sym)
t16
(lo12(sym))
t17 (or)
t3 (add)
198 (const)
Instruction selection in LLVM would be:
Mapping SDnode-> Target ISA
SDnode : selection DAG node

7. Define Target Instruction
• Define ADDI
– By ADDIForm (inherent by Instruction class)
• User could inherent and then specialize for different
kind ISA
– (outs GPR:$Rt)
• Output: 1 GPR
– (ins GPR:$Ra, imm15s:$imm)
• Inputs: 1 GPR, 1 imm15s constant
– Imm15s is a user defined operand constraint.
– “addit$Rt, $Rt, $imm”
• Assembly emit pattern

8. Selection DAG with CSE
• Have chance to deal with CSE.
+
+ +
y x8
Assume we have several instruction
With different cost.
Move reg, constant : cost 5
Add reg, reg, reg: cost 1
Addi reg, reg, constant: cost 5
There are two way to mapping instructions
R1 = y + 8; cost 5
R2 = x + 8 cost 5
R3 = R1 + R2 cost 1
Total cost 11
R1 = 8; cost 5
R2 = x + R1 cost 1
R3 = y + R1 cost 1
R4 = R2+R3 cost 1
Total cost 8
+
+ +
y x8
+
+ +
y x8

9. Selection DAG with CSE
• Dag->Target Dag selection only the one of the
factor influence optimization result.
– Even if Selection DAG not deal with CSE, we could
leave it to later pass to do it!
– In fact, LLVM move CSE consideration out of DAG
selection now.
– Currently, LLVM DAG Selection is purely greedy
selection and matching

10. Greedy DAG Selection
• LLVM would give each Target ISA “Complexity”
– Complexity big means it could cover more nodes
in the DAG
• Which means it may have chance to produce fewer
instruction if we choose Complexity big instruction
– In most of the case, few instructions could get better code
quality.

11. Greedy DAG Selection
• LLVM would give each Target ISA “Complexity”
– By default, complexity calculate by operation
number and operand kind in Target ISA
• E.g.
– Complexity (add R, R, Const) > Complexity (add R, R, R)
– Complexity (store R, [R + R << 2]) > Complexity (store R, [R])
– Complexity (add_shift) > Complexity (add)
• User also could modify their Target instruction
Complexity by AddedComplexity.

12. Greedy DAG Selection
• LLVM DAG selection is a bottom up method on
each basic block
– When try to match a node from the DAG
• LLVM will use a match table to select Target ISA
– E.g.
» Switch (Node kind)
• Case Add:
• If (op0 is reg && op1 is reg)
• If (op2 is reg) choose ADD
• If (op2is const) chose ADDI
– If Target have same semantic instructions
» Choose Complexity bigger first.

13. Instruction Matching Table
• LLVM will read Instruction pattern define in
*.td and generate Instruction matching table
– In build folder {Target}GenDAGISel.inc
• Generate by tablegen tools
• Contain the match table
• Implement as a interpreter to execute pattern match

14. Instruction Selection in dump file

15. Legalize SelectionDag
• Legalize Selection
DAG
– Legalize
• Support for the
target
– Types
• Check each Dag
Node type support
by the target
– Operations
• Check each Dag
Node operation
support by the target

16. Legalize SelectionDag
• How to specify target support types and
operations ?
– Defined in target
inherent TargetLowering constructor.
Load to 1 bit is not legal, promote to wider integer type

17. Instruction selection in LLVM
• Each SelectionDAG operation could specify as
– Legal
• The target natively supports this operation.
– Promote
• This operation should be executed in a larger type.
– Expand
• Try to expand(by llvm general code) this to other
operations, otherwise use a libcall.
– Custom
• Target should defined custom lowering method for the
operation
• Call the costom lowering method by
XXXTargetLowering::LowerOperation() target hook

18. Instruction selection in LLVM
CTPOP (counts the number of bits) for i32/i64 type is legal
Expand CTTZ (counts trailing zero) to other SDNodes for i32/i64 type
Customize BR_JT (branch to jump table)

19. Reference
• A deeper look into the LLVM code generator,
Part 1
– http://eli.thegreenplace.net/2013/02/25/a-
deeper-look-into-the-llvm-code-generator-part-1
• LLVM Legalization and Lowering
– https://wiki.aalto.fi/display/t1065450/LLVM+Legal
ization+and+Lowering
• Near-Optimal Instruction Selection on DAGs
– https://llvm.org/svn/llvm-project/www-
pubs/trunk/2008-CGO-DagISel.pdf
• Instruction Selection - Principles, Methods,