The importance of convolutional codes is well established. They are widely used to encode digital data before transmission through noisy or error-prone communication channels to reduce occurrence of errors and memory. This paper presents novel decoding technique, memoryless Hybrid Register Exchange with simulation and FPGA implementation results. It requires single register as compared to Register Exchange Method (REM) & Hybrid Register Exchange Method (HREM); therefore the data trans-fer operations and ultimately the switching activity will get reduced.
IRJET - Distributed Arithmetic Method for Complex MultiplicationIRJET Journal
This document describes a distributed arithmetic method for complex multiplication that reduces complexity compared to a regular multiplier. It presents a distributed arithmetic based complex multiplier architecture that uses lookup tables instead of actual multipliers and adders. The architecture stores pre-calculated outcomes for the real and imaginary parts of the complex multiplication in ROMs. It shifts the inputs and uses the output bits as addresses for the ROMs to perform the multiplication with less components than a traditional design. The proposed architecture is implemented in Verilog and simulated using Xilinx tools to verify its functionality for signed, unsigned and hexadecimal numbers.
Analysis of various mcm algorithms for reconfigurable rrc fir filtereSAT Journals
This document analyzes various multiple constant multiplication (MCM) algorithms for implementing reconfigurable root raised cosine (RRC) finite impulse response (FIR) filters. It compares digit based recoding, canonic sign digit (CSD), common subexpression elimination (CSE), and binary common subexpression elimination (BCSE) algorithms in terms of area, power, and speed. The results show that the BCSE algorithm provides the best performance, reducing area by up to 11.7% and power consumption compared to the other methods. The BCSE technique reuses common binary bit patterns within filter coefficients to optimize constant multiplications.
A BINARY TO RESIDUE CONVERSION USING NEW PROPOSED NON-COPRIME MODULI SETcsandit
Residue Number System is generally supposed to use co-prime moduli set. Non-coprime moduli sets are a field in RNS which is little studied. That's why this work was devoted to them. The resources that discuss non-coprime in RNS are very limited. For the previous reasons, this paper analyses the RNS conversion using suggested non-coprime moduli set.
This document discusses optimizing the gate-level area of digit-serial finite impulse response (FIR) filter designs using multiple constant multiplication (MCM) blocks. It introduces the problem of designing a digit-serial MCM operation with minimal area and presents algorithms to formalize the area optimization problem. Results show the proposed algorithms and digit-serial MCM architectures efficiently design digit-serial MCM operations and FIR filters with reduced area compared to existing approaches.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Low complexity video coding for sensor networkeSAT Journals
Abstract Modern video codecs such as H.264/AVC give state-of-the-art compression performance. However, extensive use of optimization tools makes them highly complex and hence not suitable for wireless video sensor network. In this paper an efficient video codec with substantially reduced complexity is proposed. Simulation result shows that the proposed video codec gives comparable compression performance compared to H.264/AVC but at substantially reduced computational complexity. Keywords—Low complexity coding, Sensor network, Video coding, Wavelet transform.
Faster Interleaved Modular Multiplier Based on Sign DetectionVLSICS Design
Data Security is the most important issue nowadays. A lot of cryptosystems are introduced to provide security. Public key cryptosystems are the most common cryptosystems used for securing data communication. The common drawback of applying such cryptosystems is the heavy computations which degrade performance of a system. Modular multiplication is the basic operation of common public key cryptosystems such as RSA, Diffie-Hellman key agreement (DH), ElGamal and ECC. Much research is now
directed to reduce overall time consumed by modular multiplication operation. Abd-el-fatah et al. introduced an enhanced architecture for computing modular ultiplication of two large numbers X and Y modulo given M. In this paper, a modification on that architecture is introduced. The proposed design computes modular multiplication by scanning two bits per iteration instead of one bit. The proposed design for 1024-bit precision reduced overall time by 38% compared to the design of Abd-el-fatah et al.
Effect of fiber distance on various sac ocdma detection techniqueseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IRJET - Distributed Arithmetic Method for Complex MultiplicationIRJET Journal
This document describes a distributed arithmetic method for complex multiplication that reduces complexity compared to a regular multiplier. It presents a distributed arithmetic based complex multiplier architecture that uses lookup tables instead of actual multipliers and adders. The architecture stores pre-calculated outcomes for the real and imaginary parts of the complex multiplication in ROMs. It shifts the inputs and uses the output bits as addresses for the ROMs to perform the multiplication with less components than a traditional design. The proposed architecture is implemented in Verilog and simulated using Xilinx tools to verify its functionality for signed, unsigned and hexadecimal numbers.
Analysis of various mcm algorithms for reconfigurable rrc fir filtereSAT Journals
This document analyzes various multiple constant multiplication (MCM) algorithms for implementing reconfigurable root raised cosine (RRC) finite impulse response (FIR) filters. It compares digit based recoding, canonic sign digit (CSD), common subexpression elimination (CSE), and binary common subexpression elimination (BCSE) algorithms in terms of area, power, and speed. The results show that the BCSE algorithm provides the best performance, reducing area by up to 11.7% and power consumption compared to the other methods. The BCSE technique reuses common binary bit patterns within filter coefficients to optimize constant multiplications.
A BINARY TO RESIDUE CONVERSION USING NEW PROPOSED NON-COPRIME MODULI SETcsandit
Residue Number System is generally supposed to use co-prime moduli set. Non-coprime moduli sets are a field in RNS which is little studied. That's why this work was devoted to them. The resources that discuss non-coprime in RNS are very limited. For the previous reasons, this paper analyses the RNS conversion using suggested non-coprime moduli set.
This document discusses optimizing the gate-level area of digit-serial finite impulse response (FIR) filter designs using multiple constant multiplication (MCM) blocks. It introduces the problem of designing a digit-serial MCM operation with minimal area and presents algorithms to formalize the area optimization problem. Results show the proposed algorithms and digit-serial MCM architectures efficiently design digit-serial MCM operations and FIR filters with reduced area compared to existing approaches.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Low complexity video coding for sensor networkeSAT Journals
Abstract Modern video codecs such as H.264/AVC give state-of-the-art compression performance. However, extensive use of optimization tools makes them highly complex and hence not suitable for wireless video sensor network. In this paper an efficient video codec with substantially reduced complexity is proposed. Simulation result shows that the proposed video codec gives comparable compression performance compared to H.264/AVC but at substantially reduced computational complexity. Keywords—Low complexity coding, Sensor network, Video coding, Wavelet transform.
Faster Interleaved Modular Multiplier Based on Sign DetectionVLSICS Design
Data Security is the most important issue nowadays. A lot of cryptosystems are introduced to provide security. Public key cryptosystems are the most common cryptosystems used for securing data communication. The common drawback of applying such cryptosystems is the heavy computations which degrade performance of a system. Modular multiplication is the basic operation of common public key cryptosystems such as RSA, Diffie-Hellman key agreement (DH), ElGamal and ECC. Much research is now
directed to reduce overall time consumed by modular multiplication operation. Abd-el-fatah et al. introduced an enhanced architecture for computing modular ultiplication of two large numbers X and Y modulo given M. In this paper, a modification on that architecture is introduced. The proposed design computes modular multiplication by scanning two bits per iteration instead of one bit. The proposed design for 1024-bit precision reduced overall time by 38% compared to the design of Abd-el-fatah et al.
Effect of fiber distance on various sac ocdma detection techniqueseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Braun’s Multiplier Implementation using FPGA with Bypassing Techniques.VLSICS Design
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Selection of intra prediction modes for intra frame coding in advanced video ...eSAT Journals
Abstract This paper proposes selection of Intra prediction modes for Intra frame coding in Advanced Video Coding Standard using Matlab. The proposed algorithm selects prediction modes for intra frame coding. There are nine prediction modes are there to predict the intra frame in AVC using Intra prediction,but all the prediction modes are not required for all the applications. Intra prediction is the first process of advanced video coding standard. It predicts a macro block by referring to its previous macro blocks to reduce spatial redundancy,appling all the prediction modes to predict intra frame it leads to more computational complexity is increased at the encoder of AVC. In the proposed algoriyhm, applied all the prediction modes(0-8) for prediction of intra frame but only few modes such as mode0, mode1, mode2,mode4,mode6 gives good PSNR, high comprssion ratio and low bit rate. Out of these modes mode2 gives good PSNR, compression ratio and redced bit rate, mode5, mode7 and mode8 gives lower PSNR, low compression ratio and increased bitrate compared to mode0,mode1, mode2, mode4 and mode6. The simulation results are presented using Matlab. The PSNR , compressed ratio and bit rate achived for different quantization parameters of mother daughter frames , foreman frames was presented. Keywords: AVC, PSNR, CAVLC, Macroblock, Prediction modes.
This document presents a comparative analysis of different designs for a 1-bit full adder circuit. It describes full adder designs using CMOS, TG, GDI, 9T GDI-PTL, and GDI-PTL logic. The designs are simulated in Cadence at 45nm technology with uniform transistor widths and lengths. Simulation results show that the GDI-PTL design has the lowest power delay product, making it well-suited for low-power applications. It provides satisfactory output levels with no conflicting voltage levels, using fewer transistors than CMOS or TG designs. The CMOS and TG designs have undistorted outputs but use more transistors, while the GDI and 9T designs use fewer transistors
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. TechniqueIJMER
In this paper we have implemented Radix 8 High Speed Low Power Binary Multiplier using
Modified Gate Diffusion Input(M.G.D.I) technique. Here we have used “Urdhva-tiryakbhyam”(
Vertically and crosswise ) Algorithm because as compared to other multiplication algorithms it shows
less computation and less complexity since it reduces the total number of partial products to half of it.
This multiplier at gate level can be design using any technique such as CMOS, PTL and TG but design
with new MGDI technique gives far better result in terms of area, switching delay and power
dissipation. The radix 8 High Speed Low Power Pipelined Multiplier is designed with MGDI technique
in DSCH 3.5 and layout generated in Microwind tool. The Simulation is done using 0.12μm technology
at 1.2 v supply voltage and results are compared with conventional CMOS technique. Simulation result
shows great improvement in terms of area, switching delay and power dissipation.
DESIGN OF SECURE AND RELIABLE MU-MIMO TRANSCEIVER SYSTEM FOR VEHICULAR NETWORKSIJCNCJournal
Networks have become considerably large, complex and dynamic. The configuration, operation,
monitoring, and troubleshooting of networks is a cumbersome and time-consuming task for the network
administrators as they must deal with the physical layer, underlying protocols, addressing systems, control
rules, and many other low-level details. This research paper proposes an Intent-based networking system
(IBNS) coupled with voice-assistance that can abstract the underlying network infrastructure and allow
administrators to alter its behavior by expressing intents via voice commands. The system also displays the
real-time network topology along with the highlighted intents on an interactive web application that can be
used for network diagnostics. Compared to traditional networks, the concepts of software-defined
networking (S
IRJET- The RTL Model of a Reconfigurable Pipelined MCMIRJET Journal
This document presents two Register Transfer Level (RTL) models for a reconfigurable pipelined multiple constant multiplier (MCM) architecture. The first model uses a ripple carry adder, while the second model replaces it with a carry lookahead adder. Both models are constructed using Verilog and simulated using ModelSim. Simulation results show the second model has a 3.53% higher maximum clock frequency and throughput due to the faster carry lookahead adder. It also has 3.53% lower latency but uses 1.65% more power. The second model provides faster performance with moderate increases in resource usage and power consumption.
Area and Power Efficient Up-Down counter Design by Using Full Adder ModuleIJEEE
In this paper an area and power efficient 98T Up- Down counter design has been presented by using Pass transistor logic designing technique. The proposed Up-Down counter design consist of 53 NMOS and 45 PMOS. Four PTL full adder modules has been used to design this Up-Down counter which consumes less area and power at 120 nm as compared to CMOS, TG and GDI full adder designs. The proposed Up-Down counter design is based on this area and power efficient 10 transistors PTL full adder module. The proposed Up-Down counter has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. For proposed design Power variation with respect to the supply voltage has been performed on BSIM-4 and LEVEL-3 using 120nm technology. Results show that Area of proposed PTL Up- Down counter design is 1288.4 µm2 on 120nm technology. At 1.2V input supply voltage the proposed Up-Down counter design consumes 111µW power at BSIM-4.
Performance Enhancement of MIMO-OFDM using Redundant Residue Number System IJECEIAES
Telecommunication industry requires high capacity networks with high data rates which are achieved through utilization of Multiple-Input-MultipleOutput (MIMO) communication along with Orthogonal Frequency Division Multiplexing (OFDM) system. Still, the communication channel suffers from noise, interference or distortion due to hardware design limitations, and channel environment, and to combat these challenges, and achieve enhanced performance; various error control techniques are implemented to enable the receiver to detect any possible received errors and correct it and thus; for a certain transmitted signal power the system would have lower Bit Error Rate (BER). The provided research focuses on Redundant Residue Number System (RRNS) coding as a Forward Error Correction (FEC) scheme that improves the performance of MIMO-OFDM based wireless communications in comparison with current methods as Low-Density Parity Check (LDPC) coders at the transmitter side or equalizers at receiver side. The Bit Error Rate (BER) performance over the system was measured using MATLAB tool for different simulated channel conditions, including the effect of signal amplitude reduction and multipath delay spreading. Simulation results had shown that RRNS coding scheme provides an enhancement in system performance over conventional error detection and correction coding schemes by utilizing the distinct features of Residue Number System (RNS).
Performance Analysis of Full Adder Based 2- Bit Comparator using Different De...IJEEE
This document presents a performance analysis of different design approaches for a 2-bit comparator circuit based on a full adder module. Three logic styles are evaluated: CMOS logic, Pass Transistor Logic (PTL), and Gate Diffusion Input (GDI) logic. The 2-bit comparator circuit is designed and simulated using each logic style at both 45nm and 90nm process technologies. Simulation results show that the PTL-based comparator has the smallest area of the three designs. In terms of power consumption, PTL performs best at lower voltages below 1.4V, while GDI consumes the least power above 1.4V. Overall, the PTL logic style provides the best trade-off between area
A fast fpga based architecture for measuring the distance betweenIAEME Publication
This paper presents an FPGA-based architecture for measuring the Manhattan distance between two RGB color images. The architecture takes RGB pixel values from each image as input and calculates the absolute difference between corresponding pixel values. It sums all the absolute differences and divides by the total number of pixels to obtain the normalized Manhattan distance. The architecture was implemented on a Xilinx Spartan 3 FPGA and can operate at 171.585 MHz, faster than software solutions. Experimental results demonstrating distance calculations on sample image pairs are presented. The FPGA implementation allows real-time Manhattan distance measurement for applications like image retrieval.
This document describes an efficient algorithm for two's complement multiplication. The algorithm focuses on reducing the number of partial product rows generated in the first step of multiplication. It presents a method called "sign extension prevention" that removes unequal row lengths from the partial product array. However, there is still one additional partial product row generated from the last "neg" signal of the modified Booth encoding. The algorithm then describes a quick method to calculate the two's complement of a number by selectively complementing bits based on "conversion signals". This allows generating the two's complement while also producing the other partial products, removing the need for the extra row from the last "neg" signal.
IRJET- Data Embedding using Image SteganographyIRJET Journal
This document presents a method for secure communication using both steganography and cryptography techniques. It discusses embedding encrypted text into an image using discrete wavelet transform (DWT). Specifically, it first encrypts a text message using the advanced encryption standard (AES) algorithm. It then embeds the encrypted text into an image by applying DWT to decompose the image into sub-bands and hiding the data in the high frequency sub-bands. MATLAB is used to implement a graphical user interface that allows a sender to encrypt a message, embed it into an image, and send the stego-image to a receiver. The receiver interface extracts the encrypted text from the stego-image and decrypts it using AES. The method aims to
The International Journal of Engineering and Science (The IJES)theijes
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
IRJET- Implementation of FIR Filter using Self Tested 2n-2k-1 Modulo AdderIRJET Journal
This document presents a novel algorithm and VLSI implementation for a modulo 2n-2k-1 adder. The proposed modulo adder structure has four modules: pre-processing, carry generation, carry modification, and sum calculation. It aims to reduce area and delay compared to traditional modulo adders. The proposed adder is used to generate random numbers with a long period suitable for cryptography. It is also used to implement a finite impulse response (FIR) filter to demonstrate better performance than a normal FIR filter. Simulation results show the proposed FIR filter using the modulo adder has a delay of 11.21ns, less than the 26.69ns delay of a conventional FIR filter.
The document discusses digital logic circuits and their components. It begins with an introduction to logic gates, which are the basic building blocks of digital circuits. Common logic gates like AND, OR, NOT, NAND, NOR, XOR and XNOR are described along with their truth tables. Boolean algebra is then introduced as the mathematical system used to analyze and design digital logic circuits. Important concepts in boolean algebra like boolean functions, identities and logic simplification are covered. The document concludes by describing Karnaugh maps, a graphical technique used to simplify boolean functions into their minimum logic gate implementations.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design and Performance Analysis of Convolutional Encoder and Viterbi Decoder ...IJERA Editor
In digital communication forward error correction methods have a great practical importance when channel is
noisy. Convolutional error correction code can correct both type of errors random and burst. Convolution
encoding has been used in digital communication systems including deep space communication and wireless
communication. The error correction capability of convolutional code depends on code rate and constraint
length. The low code rate and high constraint length has more error correction capabilities but that also
introduce large overhead. This paper introduces convolutional encoders for various constraint lengths. By
increasing the constraint length the error correction capability can be increased. The performance and error
correction also depends on the selection of generator polynomial. This paper also introduces a good generator
polynomial which has high performance and error correction capabilities.
An Efficient Reconfigurable Filter Design for Reducing Dynamic PowerEditor IJCATR
This paper presents an architectural view of designing a digital filter. The main idea is to design a reconfigurable filter for reducing dynamic
power consumption. By considering the input variation’s we reduce the order of the filter considering the coefficient are fixed. The filter is implemented
using mentor graphics using TSMC .18um technology. The power consumption is decreased in the rate of 16% from the conventional model with a slight
increase in area overhead. If the filter coefficients are fixed then the power can be reduced up to 18% and the area overhead can also be reduced from the
reconfigurable architecture.
Design and implementation of log domain decoder IJECEIAES
Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs a high data rate with very low BER.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Braun’s Multiplier Implementation using FPGA with Bypassing Techniques.VLSICS Design
The developing an Application Specific Integrated Circuits (ASICs) will cost very high, the circuits should be proved and then it would be optimized before implementation. Multiplication which is the basic building block for several DSP processors, Image processing and many other. The Braun multipliers can easily be implemented using Field Programmable Gate Array (FPGA) devices. This research presented the comparative study of Spartan-3E, Virtex-4, Virtex-5 and Virtex-6 Low Power FPGA devices. The implementation of Braun multipliers and its bypassing techniques is done using Verilog HDL. We are proposing that adder block which we implemented our design (fast addition) and we compared the results of that so that our proposed method is effective when compare to the conventional design. There is the reduction in the resources like delay LUTs, number of slices used. Results are showed and it is verified using the Spartan-3E, Virtex-4 and Virtex-5 devices. The Virtex-5 FPGA has shown the good performance as compared to Spartan-3E and Virtex-4 FPGA devices.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Selection of intra prediction modes for intra frame coding in advanced video ...eSAT Journals
Abstract This paper proposes selection of Intra prediction modes for Intra frame coding in Advanced Video Coding Standard using Matlab. The proposed algorithm selects prediction modes for intra frame coding. There are nine prediction modes are there to predict the intra frame in AVC using Intra prediction,but all the prediction modes are not required for all the applications. Intra prediction is the first process of advanced video coding standard. It predicts a macro block by referring to its previous macro blocks to reduce spatial redundancy,appling all the prediction modes to predict intra frame it leads to more computational complexity is increased at the encoder of AVC. In the proposed algoriyhm, applied all the prediction modes(0-8) for prediction of intra frame but only few modes such as mode0, mode1, mode2,mode4,mode6 gives good PSNR, high comprssion ratio and low bit rate. Out of these modes mode2 gives good PSNR, compression ratio and redced bit rate, mode5, mode7 and mode8 gives lower PSNR, low compression ratio and increased bitrate compared to mode0,mode1, mode2, mode4 and mode6. The simulation results are presented using Matlab. The PSNR , compressed ratio and bit rate achived for different quantization parameters of mother daughter frames , foreman frames was presented. Keywords: AVC, PSNR, CAVLC, Macroblock, Prediction modes.
This document presents a comparative analysis of different designs for a 1-bit full adder circuit. It describes full adder designs using CMOS, TG, GDI, 9T GDI-PTL, and GDI-PTL logic. The designs are simulated in Cadence at 45nm technology with uniform transistor widths and lengths. Simulation results show that the GDI-PTL design has the lowest power delay product, making it well-suited for low-power applications. It provides satisfactory output levels with no conflicting voltage levels, using fewer transistors than CMOS or TG designs. The CMOS and TG designs have undistorted outputs but use more transistors, while the GDI and 9T designs use fewer transistors
Design and Implementation of 8 Bit Multiplier Using M.G.D.I. TechniqueIJMER
In this paper we have implemented Radix 8 High Speed Low Power Binary Multiplier using
Modified Gate Diffusion Input(M.G.D.I) technique. Here we have used “Urdhva-tiryakbhyam”(
Vertically and crosswise ) Algorithm because as compared to other multiplication algorithms it shows
less computation and less complexity since it reduces the total number of partial products to half of it.
This multiplier at gate level can be design using any technique such as CMOS, PTL and TG but design
with new MGDI technique gives far better result in terms of area, switching delay and power
dissipation. The radix 8 High Speed Low Power Pipelined Multiplier is designed with MGDI technique
in DSCH 3.5 and layout generated in Microwind tool. The Simulation is done using 0.12μm technology
at 1.2 v supply voltage and results are compared with conventional CMOS technique. Simulation result
shows great improvement in terms of area, switching delay and power dissipation.
DESIGN OF SECURE AND RELIABLE MU-MIMO TRANSCEIVER SYSTEM FOR VEHICULAR NETWORKSIJCNCJournal
Networks have become considerably large, complex and dynamic. The configuration, operation,
monitoring, and troubleshooting of networks is a cumbersome and time-consuming task for the network
administrators as they must deal with the physical layer, underlying protocols, addressing systems, control
rules, and many other low-level details. This research paper proposes an Intent-based networking system
(IBNS) coupled with voice-assistance that can abstract the underlying network infrastructure and allow
administrators to alter its behavior by expressing intents via voice commands. The system also displays the
real-time network topology along with the highlighted intents on an interactive web application that can be
used for network diagnostics. Compared to traditional networks, the concepts of software-defined
networking (S
IRJET- The RTL Model of a Reconfigurable Pipelined MCMIRJET Journal
This document presents two Register Transfer Level (RTL) models for a reconfigurable pipelined multiple constant multiplier (MCM) architecture. The first model uses a ripple carry adder, while the second model replaces it with a carry lookahead adder. Both models are constructed using Verilog and simulated using ModelSim. Simulation results show the second model has a 3.53% higher maximum clock frequency and throughput due to the faster carry lookahead adder. It also has 3.53% lower latency but uses 1.65% more power. The second model provides faster performance with moderate increases in resource usage and power consumption.
Area and Power Efficient Up-Down counter Design by Using Full Adder ModuleIJEEE
In this paper an area and power efficient 98T Up- Down counter design has been presented by using Pass transistor logic designing technique. The proposed Up-Down counter design consist of 53 NMOS and 45 PMOS. Four PTL full adder modules has been used to design this Up-Down counter which consumes less area and power at 120 nm as compared to CMOS, TG and GDI full adder designs. The proposed Up-Down counter design is based on this area and power efficient 10 transistors PTL full adder module. The proposed Up-Down counter has been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. For proposed design Power variation with respect to the supply voltage has been performed on BSIM-4 and LEVEL-3 using 120nm technology. Results show that Area of proposed PTL Up- Down counter design is 1288.4 µm2 on 120nm technology. At 1.2V input supply voltage the proposed Up-Down counter design consumes 111µW power at BSIM-4.
Performance Enhancement of MIMO-OFDM using Redundant Residue Number System IJECEIAES
Telecommunication industry requires high capacity networks with high data rates which are achieved through utilization of Multiple-Input-MultipleOutput (MIMO) communication along with Orthogonal Frequency Division Multiplexing (OFDM) system. Still, the communication channel suffers from noise, interference or distortion due to hardware design limitations, and channel environment, and to combat these challenges, and achieve enhanced performance; various error control techniques are implemented to enable the receiver to detect any possible received errors and correct it and thus; for a certain transmitted signal power the system would have lower Bit Error Rate (BER). The provided research focuses on Redundant Residue Number System (RRNS) coding as a Forward Error Correction (FEC) scheme that improves the performance of MIMO-OFDM based wireless communications in comparison with current methods as Low-Density Parity Check (LDPC) coders at the transmitter side or equalizers at receiver side. The Bit Error Rate (BER) performance over the system was measured using MATLAB tool for different simulated channel conditions, including the effect of signal amplitude reduction and multipath delay spreading. Simulation results had shown that RRNS coding scheme provides an enhancement in system performance over conventional error detection and correction coding schemes by utilizing the distinct features of Residue Number System (RNS).
Performance Analysis of Full Adder Based 2- Bit Comparator using Different De...IJEEE
This document presents a performance analysis of different design approaches for a 2-bit comparator circuit based on a full adder module. Three logic styles are evaluated: CMOS logic, Pass Transistor Logic (PTL), and Gate Diffusion Input (GDI) logic. The 2-bit comparator circuit is designed and simulated using each logic style at both 45nm and 90nm process technologies. Simulation results show that the PTL-based comparator has the smallest area of the three designs. In terms of power consumption, PTL performs best at lower voltages below 1.4V, while GDI consumes the least power above 1.4V. Overall, the PTL logic style provides the best trade-off between area
A fast fpga based architecture for measuring the distance betweenIAEME Publication
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This document describes an efficient algorithm for two's complement multiplication. The algorithm focuses on reducing the number of partial product rows generated in the first step of multiplication. It presents a method called "sign extension prevention" that removes unequal row lengths from the partial product array. However, there is still one additional partial product row generated from the last "neg" signal of the modified Booth encoding. The algorithm then describes a quick method to calculate the two's complement of a number by selectively complementing bits based on "conversion signals". This allows generating the two's complement while also producing the other partial products, removing the need for the extra row from the last "neg" signal.
IRJET- Data Embedding using Image SteganographyIRJET Journal
This document presents a method for secure communication using both steganography and cryptography techniques. It discusses embedding encrypted text into an image using discrete wavelet transform (DWT). Specifically, it first encrypts a text message using the advanced encryption standard (AES) algorithm. It then embeds the encrypted text into an image by applying DWT to decompose the image into sub-bands and hiding the data in the high frequency sub-bands. MATLAB is used to implement a graphical user interface that allows a sender to encrypt a message, embed it into an image, and send the stego-image to a receiver. The receiver interface extracts the encrypted text from the stego-image and decrypts it using AES. The method aims to
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The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
IRJET- Implementation of FIR Filter using Self Tested 2n-2k-1 Modulo AdderIRJET Journal
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The document discusses digital logic circuits and their components. It begins with an introduction to logic gates, which are the basic building blocks of digital circuits. Common logic gates like AND, OR, NOT, NAND, NOR, XOR and XNOR are described along with their truth tables. Boolean algebra is then introduced as the mathematical system used to analyze and design digital logic circuits. Important concepts in boolean algebra like boolean functions, identities and logic simplification are covered. The document concludes by describing Karnaugh maps, a graphical technique used to simplify boolean functions into their minimum logic gate implementations.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Design and Performance Analysis of Convolutional Encoder and Viterbi Decoder ...IJERA Editor
In digital communication forward error correction methods have a great practical importance when channel is
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communication. The error correction capability of convolutional code depends on code rate and constraint
length. The low code rate and high constraint length has more error correction capabilities but that also
introduce large overhead. This paper introduces convolutional encoders for various constraint lengths. By
increasing the constraint length the error correction capability can be increased. The performance and error
correction also depends on the selection of generator polynomial. This paper also introduces a good generator
polynomial which has high performance and error correction capabilities.
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reconfigurable architecture.
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International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation of a bit error rate tester of a wireless communication system ...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
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IRJET-Error Detection and Correction using Turbo CodesIRJET Journal
This document summarizes a research paper on using turbo codes for error detection and correction. It discusses:
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2) Decoding is done iteratively using maximum log-map or log-map algorithms to calculate reliability metrics and soft outputs for error correction.
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High Speed Low-Power Viterbi Decoder Using Trellis Code ModulationMangaiK4
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A Configurable and Low Power Hard-Decision Viterbi Decoder in VLSI ArchitectureIRJET Journal
This document describes a configurable and low power VLSI architecture for a hard-decision Viterbi decoder. It proposes a design that can be configured for different numbers of traceback steps (N) by adjusting traceback parameters without major modifications to the register transfer level design. The design aims to consume low power. It was synthesized in Xilinx and showed good results for operational speed and area consumption when tested for N=32 and N=64 traceback steps. Viterbi decoding is an important error correction technique that involves convolutional encoding, transmission with potential errors, and decoding using the Viterbi algorithm. Low power is a priority for Viterbi decoders due to their power consumption.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A Novel Alamouti STBC Technique for MIMO System Using 16- QAM Modulation and ...IJERA Editor
The wireless communication is the emerging field of research among communication researchers and they are
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media. In this paper the wireless system is simulated with the application of Alamouti space time block codes
(STBC) with MIMO and MISO configurations to compare the results. The modulation technique used here is
16-QAM which is giving better results than other counterparts and to enhance the performance of the system i.e.
to reduce the effect of errors on data we have applied a moving average filter(MAF). The performance of the
system is shown with the simulation results with variable data sizes and found that the proposed approach is
better for the system.
The efficient interleaving of digital-video-broadcasting-satellite 2nd genera...TELKOMNIKA JOURNAL
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High Speed Low Power Veterbi Decoder Design for TCM Decodersijsrd.com
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Design and implementation of address generator for wi max deinterleaver on fpgaeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
This document analyzes and models the Enhanced Data rates for GSM Evolution (EDGE) mobile communication system. It develops a MATLAB simulation of the EDGE system to model channel coding, modulation, interleaving, burst building, multipath fading channels, channel estimation and detection. The simulation tests the system over additive white Gaussian noise and Rayleigh fading channels. Results show received signal quality decreases with lower signal-to-noise ratio, and fading channels require higher SNR to achieve the same performance as non-fading channels.
NON-STATISTICAL EUCLIDEAN-DISTANCE SISO DECODING OF ERROR-CORRECTING CODES OV...IJCSEA Journal
In this paper we describe novel non-statistical Euclidean distance soft-input, soft-output (SISO) decoding algorithms for the three currently most important error-correcting codes: the low-density parity-check (LDPC), turbo and polar codes. The metric is squared Euclidean distance, and the decoders operate using an antilog-log (AL) process. We have investigated the simulated bit-error rate (BER) performance of these non-statistical algorithms on three channel models: the additive White Gaussian noise (AWGN), the Rayleigh fading and Middleton’s Class-A impulsive noise channels, and compare them with the BER performances of the corresponding statistical decoding algorithms for the three codes and channels. In all cases the performance over the AWGN channel of the non-statistical algorithms is almost the same or slightly better than that of the statistical algorithms. In some cases the performance over the two nonGaussian channels of the non-statistical algorithms is worse than that of the statistical algorithms, but the use of a simple signal amplitude limiter placed before the decoder input significantly improves the actual and relative performances of the algorithms. Thus there is no performance loss, and sometimes a significant performance gain, for the proposed decoding algorithms. A major advantage of our algorithms is that estimation of the channel signal-to-noise ratio is not required, which in practice simplifies system implementation. In addition, we have found that the processing complexity of the non-statistical algorithms is similar or slightly less than that of the corresponding statistical algorithms, and is significantly less for the LDPC codes over all of the channels.
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It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this paper. We propose a pre-computation architecture incorporated with -algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as 70% without performance loss, while the degradation in clock speed is negligible.
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FPGA IMPLEMENTATION OF SOFT OUTPUT VITERBI ALGORITHM USING MEMORYLESS HYBRID REGISTER EXCHANGE METHOD
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.3, September 2011
DOI : 10.5121/vlsic.2011.2304 51
FPGA IMPLEMENTATION OF SOFT OUTPUT
VITERBI ALGORITHM USING MEMORYLESS HYBRID
REGISTER EXCHANGE METHOD
R .D. Kadam1
and S. L. Haridas2
1
Department of Electronics and Telecomm. BDCE, Sevagram, RTM Nagpur University,
India
rdk_arvi@rediffmail.com
2Department of Electronics and Telecomm. BDCE, Sevagram, RTM Nagpur University,
India
slhlec@rediffmail.com
ABSTRACT
The importance of convolutional codes is well established. They are widely used to encode digital data
before transmission through noisy or error-prone communication channels to reduce occurrence of errors
and memory. This paper presents novel decoding technique, memoryless Hybrid Register Exchange with
simulation and FPGA implementation results. It requires single register as compared to Register Exchange
Method (REM) & Hybrid Register Exchange Method (HREM); therefore the data trans-fer operations and
ultimately the switching activity will get reduced.
KEYWORDS
Traceback method, Register Exchange Method, Hybrid Register Exchange Method, Memoryless HREM.
1. INTRODUCTION
The task facing the designer of a digital communication system is that of providing transmitting
information from one end of the system at a rate and a level of reliability and quality that are
acceptable to the user at the other end. Convolutional encoding with Viterbi decoding is a
technique that is particularly suited to a channel in which the transmitted signal is corrupted
mainly by additive white Gaussian noise (AWGN). Viterbi decoding was developed by Andrew
J. Viterbi in 1967 [1]. As it was recognized by early 1970’s, the algorithm was a maximum
likelihood decision device for any symbol sequence that could be modeled as a state diagram [2].
Then in 1971 viterbi published another paper [3] focusing on convolutional codes, it begins with
an elementary presentation of fundamental properties and structure of convolutional codes and
proceeds with the development of maximum likelihood decoder. Since then, other researchers
have expanded on his work by finding good convolutional codes, exploring the performance
limits of the technique [4] and varying decoder design parameters to optimize the implementation
of the technique for hardware and software. They are widely used to encode digital data before
transmission through noisy or error prone communication channels to reduce occurrence of error.
The traceback (other is register exchange) method is used as a data decoding technique offers
reduced hardware complexity with longer latency as the trades off cyper et al [5] first present a
algorithm for implementing a traceback survivor memory unit (SMU), which turned to be a
generalization of the implementation is used in [6]. The hardware complexity of a viterbi decoder
is proportional to the number of states in the trellis [7]. In order to make the Viterbi algorithm a
practical decoding techniques certain refinement were made on the basis algorithm. The viterbi
algorithm uses the trellis diagram to decode an input sequence [8] is a dynamic programming
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.3, September 2011
52
algorithm for finding the shortest path through a trellis. In case of soft decision technique,
variation of the signal at the output of the demodulator are sampled and quantized, soft output
viterbi algorithm accepts and delivers soft sample values and can be regarded as a device for
improving the SNR [9], BMU finds the equivalent branch metric using correction between the
received sample values and the expected symbols and add compared select (ACS) unit perform
cumulative addition of branch metric to generate equivalent state metric, which multiple
operation results in complex control logic. The two decoding methods called modified traceback
and Hybrid register exchange method was proposed in [10]. A short overview of a soft input
viterbi decoder implementation in field programmable gate array (FPGA) for code division
multiple access (CDMA) wireless communication system is presented in [11]. It is well known
that data transmission over wireless channels are affected by attenuation, distortion, interference
and noise which affect the receiver’s ability to receive correct information. Particularly for
terrestrial cellular telephony, the interference suppression feature of CDMA can result in a many-
fold increase in capacity with multiple access techniques were not as analog and even competing
digital techniques [12].
In the following sections the coder used, system component, various decoding techniques and
finally the proposed new decoding technique with simulation and FPGA results will be described.
2. CONVOLUTION CODES
Convolution codes are well described in the literature [1], [3]. They are commonly specified by
three Parameters; (n, k, m), where: n is the number of output bits, k is the number of input bits,
and m is the number of shift register stages of the coder. The constraint length K of the code
represents the number of bits in the encoder memory that affect the generation of the n output bits
and is defined as K = m + 1. The code rate r of the code is a measure of the code efficiency and is
defined by r = k/n.
2.1. Structure of the convolutional code:
Figure 1 show the convolutional encoder structure (3, 1, 2) used in this paper and is built from its
parameters. It consists of 2 (m=2) shift register stages and two modulo-3 adders (n = 3) giving the
outputs of the encoder. The rate of the code is r = 1/3. The minimum distance of the code is dmin =
8. The outputs of the adders are sampled sequentially yielding the code symbols. The total
number p of bit symbols is given by p = n (b + m) where b is the total number of bits of
information [8].
The outputs Y0, Y1 and Y2 of the adders are governed by the following generator polynomials.
The generator polynomial for the output Y0 and Y1 is given by g0(x) = g1(x) = 1 + x + x2
the
generator polynomial for the output Y2 is given by g2(x) = 1 + x2
. g0(x), g1(x) and g2 (x) select the
shift register stages bits to be added to give the outputs of the encoder which are, for the case of
(3, 1, 2) encoder as follow. The polynomials give the code its unique error protection quality.
Y2 = U0 U2 ----------------1
Y1 = U0 U1 U2 ----------------2
Y0 = U0 U1 U2 ----------------3
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.3, September 2011
53
Figure 1. The 1/3 Convolutional Encoder
3. BLOCK DIAGRAM OF VITERBI DECODER
In this paper, the viterbi decoder is designed and implemented aims for 3GPP standard. The
diagram of proposed architecture is shown in figure 2. It is composed of branch metric unit
(BMU), add compare select unit (ACSU), survival memory unit (SMU), and a decoding unit.
3.1. Branch Metric Unit (BMU)
BMU works for calculating the branch metrics according to received sequence. For three 3-bit
soft decision input bits (i0, i1, i2) each ranging from -3 to +3, eight 5-bit branch metrics are
generated. The decision bits are represented in the two’s complement representation. The BMU
perform simple add; subtract operations on the input bits to generate the output. For example the
branch metric for the state transition which produces the binary output (010) is i0 - i1 + i2. The
BMU performs the computations, as represented in table 1. The output of the BMU is still in a
two’s complement format. The bit serial format of the branch metrics is generated by the parallel
to serial module at the output of the BMU, as shown in Figure 3. The bit serial format of the BMs
is then fed into the ACSU. In the VA for decoding convolutional codes, the squared Euclidean
distance is the optimum branch metric for decoding sequences that are transmitted in an AWGN
ACSUBMU SMU
Decoding Unit
In X FF1 FF0
Y0
Y1
Y2
+
+
+
+
+
+
U0 U1 U2
Figure 2. Block diagram of viterbi decoder
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channel. Multiplication operations or look up tables are required for the Viterbi algorithm to
compute the squared distances to obtain the branch metrics. However, for binary convolutional
codes, it is proven that linear distances (Hamming distances) can be used as the optimum branch
metrics. This is true for convolutional codes.
Table 1. Branch Metric
3.2. Add compare select (ACS)
The ACSU work in serial architecture style with 2 ACS as shown in figure 4, for having small
implementation area, each trellis state S at time t is a state metric SMp and SMq which is the
accumulated metric along the shortest path leading to that state.
BMU000 (i0+i1+i2) = (-3-3-3) -9
BMU001 (i0+i1-i2) = (-3-3+3) +3
BMU010 (i0-i1+i2) = (-3+3-3) -3
BMU011 (i0-i1-i2) = (-3+3+3) +3
BMU100 (-i0+i1+i2) = (+3-3-3) -3
BMU101 (-i0+i1-i2) = (+3-3+3) +3
BMU110 (-i0-i1+i2) = (+3+3-3) +3
BMU111 (-i0-i1-i2) = (+3+3+3) +9
BMU
000
BMU
001
BMU
010
BMU
011
++
BMU
011
BMU
101
BMU
100
+++ +
BMU
111
++
i0
i1
i2
Figure 3. Branch Metric Unit
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The state metrics at time can be recursively calculated in terms of the state metrics of the previous
iteration as follows:
For state metric SMt
SMp = min (SMi+BMi1, SMj+BMj1),
SMq = min (SMi+BMi0, SMj+BMj0)
To demonstrate the functionality of VA, a sample input to the encoder is traced until the input is
decoded. The encoder has an input sequence, 11011000 and generates the code stream, (111, 100,
100, 000, 100, 100, 111 and 000). The VA which uses soft decision formats to decode survivor
path.
4. DECODING TECHNIQUES
4.1. Register Exchange method
In the register exchange method [2], a register assigned to each state contains information bits for
the survivor path from the initial state to the current state. In fact, the register keeps the partially
decoded output sequence along the path, as illustrated in figure 5. The register of state S1 at t = 3
contain ‘110’, which is the decoded output sequence along the hold path from the initial state.
The resister exchange approach does require the copying of all the registers at each stage. The
need to traceback is eliminated since the register of the final state contain the decoded output
sequence. However, this approach results in complex hardware due to the need to copy the
contents of all the register in a stage to the next stage. At last stage, the decoded output sequence
is the one that is stored in the survivor path register S0, the register assigned to the state with the
minimum Path Metric. Since the Register Exchange method does not need tracing back, it is
faster. However, the RE method does require the copying of all the registers at each stage.
Figure 5. Register Exchange Approach
S2
SMSMj
SMi SMS1
S0 S0
Figure 4. ACSU Butterfly
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4.2. Hybrid Register Exchange Method
The main drawback of register exchange method is its frequent switching activity and long
constraint length. One of the promising solutions to reduce the switching activity can be achieved
by combining the REM and TB techniques [4]. The initial state can be first traced back through
an m cycle, and then transfer the content of initial state to the current state and the next m bits of
the register is the m bits of current state itself.
Figure 6. Hybrid Register Exchange Approach
4.3. Memoryless Register Exchange Method
The RE approach generates the decoded bits in the correct order. The decoded bits are produced,
and then read out from the decoder. Thus, a memory free viterbi decoder can be implemented by
solely resetting the encoder contents for each L bits that are encoded. The new VD
implementation is called the memoryless viterbi decoder (MLVD). Since the MLVD needs to
track only one row, the MLVD requires only one pointer to track the current position of the
decoder in the trellis. If the initial state is zero, then only the first row of memory is needed. In
other words, the storage of the decoded bits is necessary in order to choose only one row of
memory at the end to represent the actual decoded bits. If the required row of memory is
predetermined, and then there is no need for the storage of the other rows as shown in figure 7.
Figure 7. Memoryless REM
4.4. Memoryless Hybrid Register Exchange method
The MLVD keeps track of the current state position of the decoder in the memory unit as shown
in Figure 8. It makes use of the fact that the bit appended to each row of memory is exactly the bit
that is shifted into the pointer to form the new pointer to that row of memory [13]. To show the
00 01 11 10 01 11 10 00 00
t=0
1
t=1
11
t=2
110
t=3
1101
t=4
11011
t=5
110110
t=6
1101100
t=7
11011000
t=8
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functionality, K = 3 a (four states) and rate = 1/3 convolutional encoder (g2 = 101, g1 = 111, g0 =
111) is employed to encode the input sequence of (11011000). The code stream (111, 100, 100,
000, 100, 100, 111 and 000) is generated and transmitted over a channel. The noisy code stream
(111, 110, 101, 000, 100, 100, 111 and 000) for example is received at the decoder. The
underlined bits are incorrect because of the noise encountered during transmission. Applying the
MLVD method result in the successive values for the pointer and row of memory for the decoded
data over time. The pointer contains the current state of the decoder (m bits). The data at memory
is the pointer value at that instant. Every time the digit get decode. It is reset to zero (the initial
state of the encoder) after decoded last bits. After every ‘m’ cycles the pointer content and
memory contents are upend, so the switching will get reduced.
Figure 8. Memoryless Hybrid Register Exchange Method
5. SIMULATION RESULT FOR MEMORYLESS HREM
Figure 9 shows the simulation result for memoryless HREM, using pointer implementation.
Encoding the data of 8 bit as adding 2 bit noise error. We get the result after 14 clock pulse unit
as shown in Figure. It is same decoding input data to decode the serially output data. It shows the
noise of two bits can be corrected by the decoder since it has free distance of 8.
Fig.9. Simulation Result for memoryless hybrid register exchange method
6. FPGA Implementation
To prepare the MLVD using Hybrid Register Exchange processing VHDL design that is
implemented on the FPGA, the design is synthesized by using Synopsys tool. Then, the design is
imported into Xilinx tools for the mapping routing, then a VHDL file with timing information is
11 01 10 00
11
t=2
1101
t=4
110110
t=6
11011000
t=8
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re-simulated for the timing verification. Afterward, the MLVDs design is downloaded to a
xs2s200 Xilinx chip. The MLVDs consumes only 2% of the total slices of the xs2s200,
comprising a total of 2352 gates. The design consumes 16 I/O bits.
All the decoding techniques are implemented and compared on the same platform.
Table 2. FPGA Simulation Report
Device Utilization REM HREM MLREM MLHREM
Number of Slices 254outof2352
10%
220 out of 2352
9%
60 out of 2352
2%
63 out of 2352
2%
Number of Slice
Flip Flop
144outof4704
3%
142 out of 4704
3%
68 out of 4704
1%
68 out of 4704
1%
Number of 4 input
LUTs
456outof4704
9%
390 out of 4704
8%
85 out of 4704
1%
83 out of 4704
1%
Number of bounded
IOBs
16outof 144
11%
16 out of 144
11%
16outof 144
11%
16 out of 144
11%
Registers 87 85 47 47
Multiplexers 44 3 6 6
Adder/ Substractor 21 21 13 13
Comparators 9 9 3 3
7. CONCLUSION
The MLVD using HREM is a memoryless implementation of the VA, and successfully decodes
the continuous data encoded by a convolutional encoder. The latency is only 2 data bits. The new
implementation is realized by applying the pointer concept to the HREM implementation, and by
using trellis truncation for every bit encoded. It is found that the new proposed decoding
technique requires lesser hardware as compared to REM, HREM and memoryless REM
techniques. The maximum throughput is 56 Mbps which is still more than 2Mbps which is
requirement of wireless communication. Increasing the MLVDs performance by increasing the
constraint length is still to be investigated. So the memoryless hybrid register exchange approach
can be used in place of traceback, register exchange for decoding of data.
References
[1] A. J. Viterbi, “Error Bounds on Convolutional Codes and an Asymptotically Optimum Decoding
Algorithm” Information and Control, 25(3), pp 260-269, April 1967.
[2] “A Personal History of the Viterbi algorithm” IEEE Signal Processing Magazine, July 2006.
[3] “Convolutional codes and their performance in communication systems” Andrew Viterbi, IEEE
trans. On communication technology, vol. com-19, 1971.
[4] G. Forney, “Convolutional codes II. Maximum - likelihood decoding.” Information and Control,
25(3), pp 222-266, July 1974
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[5] “Generalized Traceback Techniques for Survivor Memory Management in the Viterbi Algorithm”,
Robert Cypher, C. Bernard Shung, IEEE 1990.
[6] H.A. Bustamante, I. Kang, C. Nguyen and R.E. Peile,” Stanford Telecomm design of a convolutional
decoder,” In MILCOM 89,Boston MA, October 1080 pp. 171-178.
[7] “A Low power Viterbi Decoder Design for wireless communication Application”, Samirkumar
Ranpara, Dong Sam Ha, IEEE 1999.
[8] A. J Viterrbi, J.K Omura, “Principals of digital communication”, McGraw Hill, Inc, 1979.
[9] “A Viterbi Algorithm with soft decision outputs and its application”, Joachim Hagenauer, Peter
Hoeher, IEEE 1989.
[10] “Prof. S. L. Haridas, Dr. N. K. Choudhari,” Design of Viterbi Decoder with Modified Traceback
and Hybrid Register Exchange Processing ICAC3’09.
[11] “FPGA Implementation of soft Input Viterbi Decoder for CDMA2000 System” Milos Pilipovic,
Marija Tadic, Novi Sad, Telefore 2008.
[12] “On the capacity of a cellular CDMA system “Klein S. Gilhousen, Irwin M. Jacobs, Roberto Padovani,
Andrew Lindsay A. Weaver, Jr Charles E. Wheatley 1211, IEEE trans. On vehicular technology,
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Gilhousen, Butch, Weaver, Robert Padovani, Houtan DSehesh, Qualcomm Inc, San Diego, IUEEE
1992.
[13] Memoryless Viterbi Decoder Dalia A. El-Dib, Member, IEEE and M. I. Elmasry, Fellow, EXPRESS
BRIEFS, VOL. 52, NO. 12, IEEE 2005
Authors
Ravindra D. Kadam is pursuing M.Tech in Electronics Engineering from
RTM Nagpur University, Nagpur, India. He received CDAC in Pune, India in
1999. He received his B.E. degree in Electronics Engineering from RTM
Nagpur University, Nagpur in year 1997. He is currently working as Assistant
Professor in the Department of Electronics and Telecomm. Engineering ,
BDCOE, Sevagram, Wardha, M.S., India. His research interests include
computer networks and VLSI systems.
Sanjay L. Haridas received B.E. degree in Electronics Engineering from
RTM Nagpur University, Nagpur in year 1988 and M.Tech in Electronics
Engineering from VNIT, Nagpur in 1995. He is Professor in the Department of
Electronics and Telecommunication Engineering, BDCOE, Sevagram,
Wardha, M.S., India. His research interests are VLSI circuit design and Digital
Communiation.