This document summarizes a research paper that proposes a new binary tree algorithm for implementing a Huffman decoder. It begins by explaining the disadvantages of using an array data structure to represent the Huffman decoding tree and how the proposed binary tree method requires less memory. The proposed decoder is then implemented using ASIC and FPGA design tools. Performance metrics like power, area, and number of registers are obtained and compared between the ASIC and FPGA implementations. Simulation results show that the ASIC implementation has lower power consumption than the FPGA version. In conclusion, the binary tree algorithm is shown to improve memory usage for Huffman decoding.