The document discusses addressing modes in computers. It defines addressing modes as the different ways of specifying the location of an operand in an instruction. It then describes 10 common addressing modes: implied, immediate, register, register indirect, autoincrement/autodecrement, direct, indirect, relative, indexed, and base register. Each mode is explained with an example to illustrate how the effective address is calculated. Addressing modes provide versatility for programming by enabling features like pointers, loop counters, data indexing, and program relocation while reducing the number of bits needed in instruction addresses.
BASIC INFORMATION OF ARCHITECTURE OF MICRO-CONTROLLER 8051 AS PER GTU SYLLABUS. Please Comment if u Like.. n Give u r feedback..
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BASIC INFORMATION OF ARCHITECTURE OF MICRO-CONTROLLER 8051 AS PER GTU SYLLABUS. Please Comment if u Like.. n Give u r feedback..
For More Information Go to
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Describe the three main addressing modes of the PIC16 architecture di.pdfSALES97
Describe the three main addressing modes of the PIC16 architecture discussed in class. For each
of the modes include two examples. Write a PIC16 assembly program which will accomplish the
following instruction. I just want the section of assembly code which accomplishes this. Make
VAR1 =0x22. VAR1 = 0x42 + (0xF0 AND 0xAA) - (0x12 OR 0x34) Perform the above
calculation by hand, showing all your work in binary.
Solution
2 ans
)
The term addressing modes refers to the way in which the operand of an instruction is specified.
Information contained in the instruction code is the value of the operand or the address of the
result/operand. Following are the main addressing modes that are used on various platforms and
architectures.
1) Immediate Mode
The operand is an immediate value is stored explicitly in the instruction:
Example: SPIM ( opcode dest, source)
li $11, 3 // loads the immediate value of 3 into register $11
li $9, 8 // loads the immediate value of 8 into register $9
Example : (textbook uses instructions type like, opcode source, dest)
move #200, R0; // move immediate value 200 in register R0
2) Index Mode
The address of the operand is obtained by adding to the contents of the general register (called
index register) a constant value. The number of the index register and the constant value are
included in the instruction code. Index Mode is used to access an array whose elements are in
successive memory locations. The content of the instruction code, represents the starting address
of the array and the value of the index register, and the index value of the current element. By
incrementing or decrementing index register different element of the array can be accessed.
Example: SPIM/SAL - Accessing Arrays
3) Indirect Mode
The effective address of the operand is the contents of a register or main memory location,
location whose address appears in the instruction. Indirection is noted by placing the name of the
register or the memory address given in the instruction in parentheses. The register or memory
location that contains the address of the operand is a pointer. When an execution takes place in
such mode, instruction may be told to go to a specific address. Once it\'s there, instead of finding
an operand, it finds an address where the operand is located.
NOTE:
Two memory accesses are required in order to obtain the value of the operand (fetch operand
address and fetch operand value).
Example: (textbook) ADD (A), R0
(address A is embedded in the instruction code and (A) is the operand address = pointer variable)
Example: SPIM - simulating pointers and indirect register addressing
The following \"C\" code:
could be translated into the following assembly code:
Example: SPIM/SAL - - array pointers and indirect register addressing
4) Absolute (Direct) Mode
The address of the operand is embedded in the instruction code.
Example: (SPIM)
5) Register Mode
The name (the number) of the CPU register is embedded in the instruction. The register contai.
A computer instruction is a binary code that specifies a sequence of micro operations for the computer.
Instruction codes together with data are stored in memory.
The computer reads each instruction from memory and places it in a control register.
The control unit then interprets the binary code of the instruction and proceeds to execute it by issuing a sequence of micro operations.
Earliest Galaxies in the JADES Origins Field: Luminosity Function and Cosmic ...Sérgio Sacani
We characterize the earliest galaxy population in the JADES Origins Field (JOF), the deepest
imaging field observed with JWST. We make use of the ancillary Hubble optical images (5 filters
spanning 0.4−0.9µm) and novel JWST images with 14 filters spanning 0.8−5µm, including 7 mediumband filters, and reaching total exposure times of up to 46 hours per filter. We combine all our data
at > 2.3µm to construct an ultradeep image, reaching as deep as ≈ 31.4 AB mag in the stack and
30.3-31.0 AB mag (5σ, r = 0.1” circular aperture) in individual filters. We measure photometric
redshifts and use robust selection criteria to identify a sample of eight galaxy candidates at redshifts
z = 11.5 − 15. These objects show compact half-light radii of R1/2 ∼ 50 − 200pc, stellar masses of
M⋆ ∼ 107−108M⊙, and star-formation rates of SFR ∼ 0.1−1 M⊙ yr−1
. Our search finds no candidates
at 15 < z < 20, placing upper limits at these redshifts. We develop a forward modeling approach to
infer the properties of the evolving luminosity function without binning in redshift or luminosity that
marginalizes over the photometric redshift uncertainty of our candidate galaxies and incorporates the
impact of non-detections. We find a z = 12 luminosity function in good agreement with prior results,
and that the luminosity function normalization and UV luminosity density decline by a factor of ∼ 2.5
from z = 12 to z = 14. We discuss the possible implications of our results in the context of theoretical
models for evolution of the dark matter halo mass function.
Richard's entangled aventures in wonderlandRichard Gill
Since the loophole-free Bell experiments of 2020 and the Nobel prizes in physics of 2022, critics of Bell's work have retreated to the fortress of super-determinism. Now, super-determinism is a derogatory word - it just means "determinism". Palmer, Hance and Hossenfelder argue that quantum mechanics and determinism are not incompatible, using a sophisticated mathematical construction based on a subtle thinning of allowed states and measurements in quantum mechanics, such that what is left appears to make Bell's argument fail, without altering the empirical predictions of quantum mechanics. I think however that it is a smoke screen, and the slogan "lost in math" comes to my mind. I will discuss some other recent disproofs of Bell's theorem using the language of causality based on causal graphs. Causal thinking is also central to law and justice. I will mention surprising connections to my work on serial killer nurse cases, in particular the Dutch case of Lucia de Berk and the current UK case of Lucy Letby.
Comparing Evolved Extractive Text Summary Scores of Bidirectional Encoder Rep...University of Maribor
Slides from:
11th International Conference on Electrical, Electronics and Computer Engineering (IcETRAN), Niš, 3-6 June 2024
Track: Artificial Intelligence
https://www.etran.rs/2024/en/home-english/
Observation of Io’s Resurfacing via Plume Deposition Using Ground-based Adapt...Sérgio Sacani
Since volcanic activity was first discovered on Io from Voyager images in 1979, changes
on Io’s surface have been monitored from both spacecraft and ground-based telescopes.
Here, we present the highest spatial resolution images of Io ever obtained from a groundbased telescope. These images, acquired by the SHARK-VIS instrument on the Large
Binocular Telescope, show evidence of a major resurfacing event on Io’s trailing hemisphere. When compared to the most recent spacecraft images, the SHARK-VIS images
show that a plume deposit from a powerful eruption at Pillan Patera has covered part
of the long-lived Pele plume deposit. Although this type of resurfacing event may be common on Io, few have been detected due to the rarity of spacecraft visits and the previously low spatial resolution available from Earth-based telescopes. The SHARK-VIS instrument ushers in a new era of high resolution imaging of Io’s surface using adaptive
optics at visible wavelengths.
Multi-source connectivity as the driver of solar wind variability in the heli...Sérgio Sacani
The ambient solar wind that flls the heliosphere originates from multiple
sources in the solar corona and is highly structured. It is often described
as high-speed, relatively homogeneous, plasma streams from coronal
holes and slow-speed, highly variable, streams whose source regions are
under debate. A key goal of ESA/NASA’s Solar Orbiter mission is to identify
solar wind sources and understand what drives the complexity seen in the
heliosphere. By combining magnetic feld modelling and spectroscopic
techniques with high-resolution observations and measurements, we show
that the solar wind variability detected in situ by Solar Orbiter in March
2022 is driven by spatio-temporal changes in the magnetic connectivity to
multiple sources in the solar atmosphere. The magnetic feld footpoints
connected to the spacecraft moved from the boundaries of a coronal hole
to one active region (12961) and then across to another region (12957). This
is refected in the in situ measurements, which show the transition from fast
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but are applicable to near-Earth observatories.
Introduction:
RNA interference (RNAi) or Post-Transcriptional Gene Silencing (PTGS) is an important biological process for modulating eukaryotic gene expression.
It is highly conserved process of posttranscriptional gene silencing by which double stranded RNA (dsRNA) causes sequence-specific degradation of mRNA sequences.
dsRNA-induced gene silencing (RNAi) is reported in a wide range of eukaryotes ranging from worms, insects, mammals and plants.
This process mediates resistance to both endogenous parasitic and exogenous pathogenic nucleic acids, and regulates the expression of protein-coding genes.
What are small ncRNAs?
micro RNA (miRNA)
short interfering RNA (siRNA)
Properties of small non-coding RNA:
Involved in silencing mRNA transcripts.
Called “small” because they are usually only about 21-24 nucleotides long.
Synthesized by first cutting up longer precursor sequences (like the 61nt one that Lee discovered).
Silence an mRNA by base pairing with some sequence on the mRNA.
Discovery of siRNA?
The first small RNA:
In 1993 Rosalind Lee (Victor Ambros lab) was studying a non- coding gene in C. elegans, lin-4, that was involved in silencing of another gene, lin-14, at the appropriate time in the
development of the worm C. elegans.
Two small transcripts of lin-4 (22nt and 61nt) were found to be complementary to a sequence in the 3' UTR of lin-14.
Because lin-4 encoded no protein, she deduced that it must be these transcripts that are causing the silencing by RNA-RNA interactions.
Types of RNAi ( non coding RNA)
MiRNA
Length (23-25 nt)
Trans acting
Binds with target MRNA in mismatch
Translation inhibition
Si RNA
Length 21 nt.
Cis acting
Bind with target Mrna in perfect complementary sequence
Piwi-RNA
Length ; 25 to 36 nt.
Expressed in Germ Cells
Regulates trnasposomes activity
MECHANISM OF RNAI:
First the double-stranded RNA teams up with a protein complex named Dicer, which cuts the long RNA into short pieces.
Then another protein complex called RISC (RNA-induced silencing complex) discards one of the two RNA strands.
The RISC-docked, single-stranded RNA then pairs with the homologous mRNA and destroys it.
THE RISC COMPLEX:
RISC is large(>500kD) RNA multi- protein Binding complex which triggers MRNA degradation in response to MRNA
Unwinding of double stranded Si RNA by ATP independent Helicase
Active component of RISC is Ago proteins( ENDONUCLEASE) which cleave target MRNA.
DICER: endonuclease (RNase Family III)
Argonaute: Central Component of the RNA-Induced Silencing Complex (RISC)
One strand of the dsRNA produced by Dicer is retained in the RISC complex in association with Argonaute
ARGONAUTE PROTEIN :
1.PAZ(PIWI/Argonaute/ Zwille)- Recognition of target MRNA
2.PIWI (p-element induced wimpy Testis)- breaks Phosphodiester bond of mRNA.)RNAse H activity.
MiRNA:
The Double-stranded RNAs are naturally produced in eukaryotic cells during development, and they have a key role in regulating gene expression .
Nutraceutical market, scope and growth: Herbal drug technologyLokesh Patil
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Deep Behavioral Phenotyping in Systems Neuroscience for Functional Atlasing a...Ana Luísa Pinho
Functional Magnetic Resonance Imaging (fMRI) provides means to characterize brain activations in response to behavior. However, cognitive neuroscience has been limited to group-level effects referring to the performance of specific tasks. To obtain the functional profile of elementary cognitive mechanisms, the combination of brain responses to many tasks is required. Yet, to date, both structural atlases and parcellation-based activations do not fully account for cognitive function and still present several limitations. Further, they do not adapt overall to individual characteristics. In this talk, I will give an account of deep-behavioral phenotyping strategies, namely data-driven methods in large task-fMRI datasets, to optimize functional brain-data collection and improve inference of effects-of-interest related to mental processes. Key to this approach is the employment of fast multi-functional paradigms rich on features that can be well parametrized and, consequently, facilitate the creation of psycho-physiological constructs to be modelled with imaging data. Particular emphasis will be given to music stimuli when studying high-order cognitive mechanisms, due to their ecological nature and quality to enable complex behavior compounded by discrete entities. I will also discuss how deep-behavioral phenotyping and individualized models applied to neuroimaging data can better account for the subject-specific organization of domain-general cognitive systems in the human brain. Finally, the accumulation of functional brain signatures brings the possibility to clarify relationships among tasks and create a univocal link between brain systems and mental functions through: (1) the development of ontologies proposing an organization of cognitive processes; and (2) brain-network taxonomies describing functional specialization. To this end, tools to improve commensurability in cognitive science are necessary, such as public repositories, ontology-based platforms and automated meta-analysis tools. I will thus discuss some brain-atlasing resources currently under development, and their applicability in cognitive as well as clinical neuroscience.
3. Addressing mode:
The different ways in which the
location of an operand is
specified in an instruction are
addressing modes.
4. Instruction Cycle & PC :
The control unit of a computer is designed to go through an
instruction cycle that is divided into three major phases:
-Fetch the instruction.
-Decode the instruction.
-Execute the instruction.
PC (program counter) is a register that keeps track of the
instructions in the program stored in the memory. PC holds
the address of the instruction to be executed next and is
incremented each time an instruction is fetched from
memory.
5. Instruction Format:
An example of an instruction format
• Operation code field defines the operation to be performed.
• Mode field is used to locate the operands needed for the operation.
• Address field designate a memory address or a register .
but there may or may not be an address field in the
instruction . If there is an address field it designate a memory
address or processor register.
opcode Mode Address
6. Modes that need no address field:
There are different addressing modes (10)
Although most addressing modes modify the address field of
the instruction, there are two modes that need no address field
at all.
These are
Implied mode
Immediate mode
7. 1-Implied mode:
In this mode the operands are specified implicitly in
the definition of the instruction.
for example: zero address instruction in stack
organized CPU the operation type instruction do
not need an address field. The instruction
ADD
in a stack computer consists of an operation code only
with no address field .There is no need to specify
operands with an address field since all operands are
implied to be in the stack.
8. 2-Immediate Addressing Mode:
In this mode the operand itself specified in the instruction .
In other words
An immediate mode instruction has an
operand rather than an address field . The
operand field contain the actual operand to be
used.
for example:
MOV R # 20
This instruction is used to initialize a register to a
constant.
9. When the address field specify a processor register the
instruction is said to be in the register mode.
In the register mode the operands are in registers
that resides inside the CPU.
for example:
MOV R1 , R2
R2
opcode Register name
operand
10. 4-Register Indirect Mode:
In this mode the instruction specifies register in the CPU whose content give
the address of the operand in the memory.
OR
The selected register contain the address of the register rather than operand
itself .
for example:
MOV A , (R) ( this notation identify
R do not contain the
operand it contain the
R address of operand )
memory
• Used in pointers.
opcode Reg name
Memory
address
operand
11. 5-Autoincrement/Autodecrement Mode:
In this mode E.A of the operand is the content of register specified in
instruction , after / before accessing the operand the content of the
register are automatically incremented/decremented to the step size
d.
This mode is similar to the register indirect mode except that the
register is incre /decr after it’s value is used.
For example: ADD R1,(R2)+ memory
E.A=[R] 1000
E.A=[R]+d R 1001
E.A=[R]+2d 1002
• This mode is used in loop counter. 1003
opcode R
E.A(1003)
operand
12. 6-Direct Addressing Mode:
In this mode E.A / address of operand directly given I n
instruction.
In this mode the effective address is equal to the address
part of the instruction the operand resides in memory and its
address is given directly by the address field of the instruction.
for example: ADD R , 2000 E.A
r r+[2000]
opcode E.A
Operand
value
13. 7-Indirect Addressing Mode:
In this mode address field of an instruction give the address where the E.A is
stored in memory . Control fetch the instruction from memory and uses its
address part to access memory again to read the E.A.
Example:
memory
memory
opcode
Memory
address
E.A
operand
14. A few addressing modes require that the address field
of the instruction be added to the content of a specific
register in the CPU the effective address in these
modes is obtained from the following computation:
E.A = address part of the instruction
+ content of CPU register
The CPU register used in the computation may be the
PC(program counter),Index register , Base register.
15. In either case we have different
addressing modes.
These modes are:
1-Relative Address Mode
2-Indexed Addressing Mode
3-Base Register Addressing Mode
16. 8-Relative Address mode (relative to PC):
In this mode the content of the PC is added to the address part of instruction
in order to obtain the effective address.
PC
+ E.A = A + B
Instruction PC
E.A=2000+1002
E.A= 3002
opcode address(A)
B
opcode 2000
1002
17. 9-Index Addressing Mode:
In this mode the content of an index register is added
to the address part of the instruction to obtain the
effective address.
• Base Register : It is a special CPU register that contains an index value.
• Address field of the instruction defines the beginning address of data are
in memory.
• Each operand in array is stored in memory relative to the beginning
address.
• The distance b/w the beginning address and the address of the operand is
the index value stored in the register .
18. Example:
Instruction IR
1000
1000 1001 1002 1003 1004
[A]
0 1 2 3 4
E.A=1000+3
This type of address mode used to access array element.
opcode
Memory add /base
address
3
operand
19. 10-Base Register Addressing Mode:
In this mode the content of a base register is added to the
address part of the instruction to obtain the effective address.
• This mode is similar to index addressing Mode except that the
register is now called a base register instead of an index
register.
• The diff b/w these modes is in the way they are used rather
than in the way they are computed.
• An index register is assumed to hold an index number that is
relative to the address part.
• A base register is assumed to hold a base address and the
address field of the instruction give a displacement relative to
this base address.
21. Why Addressing Modes are used:
Computer use addressing mode techniques for the purpose
of giving programming versatility to the user by providing
such facilities:
1-as pointer to memory.
2-as counters for loop controls.
3-indexing of data.
4-Program relocation.
5-to reduce the number of bits in the addressing
field of the instruction.