ADC & DAC
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The document discusses analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). It explains that ADCs are used to convert analog signals to digital format for advantages like digital processing, while DACs perform the reverse conversion of digital signals back to analog format for playback. A key DAC design uses an R-2R ladder network, where resistor values create a weighted voltage ladder corresponding to digital inputs. The document analyzes this design in depth.
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ADC & DAC
- 1. ADC and DAC circuits Module 5
- 2. Introduction
- 3. Introduction * Real signals (e.g., a voltage measured with a thermocouple or a speech signal recorded with a microphone) are analog quantities, varying continuously with time.
- 4. Introduction * Real signals (e.g., a voltage measured with a thermocouple or a speech signal recorded with a microphone) are analog quantities, varying continuously with time. * Digital format offers several advantages: digital signal processing, storage, use of computers, robust transmission, etc.
- 5. Introduction * Real signals (e.g., a voltage measured with a thermocouple or a speech signal recorded with a microphone) are analog quantities, varying continuously with time. * Digital format offers several advantages: digital signal processing, storage, use of computers, robust transmission, etc. * An ADC (Analog-to-Digital Converter) is used to convert an analog signal to the digital format.
- 6. Introduction * Real signals (e.g., a voltage measured with a thermocouple or a speech signal recorded with a microphone) are analog quantities, varying continuously with time. Digital format offers several advantages: digital signal processing, storage, use of computers, robust transmission, etc. An ADC (Analog-to-Digital Converter) is used to convert an analog signal to the digital format. The reverse conversion (from digital to analog) is also required. For example, music stored in a DVD in digital format must be converted to an analog voltage for playing out on a speaker. * * *
- 7. Introduction * Real signals (e.g., a voltage measured with a thermocouple or a speech signal recorded with a microphone) are analog quantities, varying continuously with time. Digital format offers several advantages: digital signal processing, storage, use of computers, robust transmission, etc. An ADC (Analog-to-Digital Converter) is used to convert an analog signal to the digital format. The reverse conversion (from digital to analog) is also required. For example, music stored in a DVD in digital format must be converted to an analog voltage for playing out on a speaker. A DAC (Digital-to-Analog Converter) is used to convert a digital signal to the analog format. * * * *
- 8. Introduction
- 12. DAC VA VR maximum output voltage N-bit digital input analog output resolution ground digital input O DN−1 VA D2 D1 D0 O * K is proportional to the reference voltage VR . Its value depends on how the DAC is implemented.
- 13. R-2R ladder network R R R 2R 2R 2R 2R 2R A0 LSB A1 A2 A3 MSB Node Ak is connected to VR if input bit Sk is 1; else, it is connected to ground.
- 14. R-2R ladder network R R R 2R 2R 2R 2R 2R A0 LSB A1 A2 A3 MSB Node Ak is connected to VR if input bit Sk is 1; else, it is connected to ground. The original network is equivalent to R R R 2R 2R 2R 2R 2R S0VR S1VR S2VR S3VR
- 15. R-2R ladder network: Thevenin resistance R R R 2R 2R 2R 2R 2R
- 16. R-2R ladder network: Thevenin resistance R R R 2R 2R 2R 2R 2R
- 17. R-2R ladder network: Thevenin resistance R R R 2R 2R 2R 2R 2R R R R R 2R 2R 2R
- 18. R-2R ladder network: Thevenin resistance R R R 2R 2R 2R 2R 2R R R R R 2R 2R 2R
- 19. R-2R ladder network: Thevenin resistance R R R 2R 2R 2R 2R 2R R R R R 2R 2R 2R R R R 2R 2R
- 20. R-2R ladder network: Thevenin resistance R R R 2R 2R 2R 2R 2R R R R R 2R 2R 2R R R R 2R 2R
- 21. R-2R ladder network: Thevenin resistance R R R 2R 2R 2R 2R 2R R R R R 2R 2R 2R R R R 2R 2R R R 2R
- 22. R-2R ladder network: Thevenin resistance R R R 2R 2R 2R 2R 2R R R R R 2R 2R 2R R R R 2R 2R R R 2R
- 23. R-2R ladder network: Thevenin resistance R R R 2R 2R 2R 2R 2R R R R R 2R 2R 2R R R R 2R 2R R R 2R RTh = R
- 24. R-2R ladder network: VTh for S0 =1 R R R 2R 2R 2R 2R 2R VR
- 25. R-2R ladder network: VTh for S0 =1 R R R 2R 2R 2R 2R 2R VR
- 26. R-2R ladder network: VTh for S0 =1 R R R 2R R R R R VR 2 2R 2R 2R 2R 2R 2R 2R VR
- 27. R-2R ladder network: VTh for S0 =1 R R R 2R R R R R VR 2 2R 2R 2R 2R 2R 2R 2R VR
- 28. R-2R ladder network: VTh for S0 =1 R R R 2R R R R R VR 2 R R R VR 4 2R 2R 2R 2R 2R 2R 2R 2R 2R VR
- 29. R-2R ladder network: VTh for S0 =1 R R R 2R R R R R VR 2 R R R VR 4 2R 2R 2R 2R 2R 2R 2R 2R 2R VR
- 30. R-2R ladder network: VTh for S0 =1 R R R 2R R R R R VR 2 R R R VR 4 R R VR 8 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R VR
- 31. R-2R ladder network: VTh for S0 =1 R R R 2R R R R R VR 2 R R R VR 4 R R VR 8 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R VR
- 32. R-2R ladder network: VTh for S0 =1 R R R 2R R R R R VR 2 R R R VR 4 R R VR 8 VR VTh = 16 2R 2R 2R 2R 2R 2R 2R 2R 2R 2R VR
- 33. R-2R ladder network: VTh for S1 =1 R R R 2R 2R 2R 2R 2R VR
- 34. R-2R ladder network: VTh for S1 =1 R R R 2R 2R 2R 2R 2R VR
- 35. R-2R ladder network: VTh for S1 =1 R R R 2R R R 2R 2R 2R 2R VR 2R 2R 2R 2R VR
- 36. R-2R ladder network: VTh for S1 =1 R R R 2R R R 2R 2R 2R 2R VR 2R 2R 2R 2R VR
- 37. R-2R ladder network: VTh for S1 =1 R R R 2R R R 2R R R R VR 2 2R 2R 2R 2R 2R VR 2R 2R 2R 2R VR
- 38. R-2R ladder network: VTh for S1 =1 R R R 2R R R 2R R R R VR 2 2R 2R 2R 2R 2R VR 2R 2R 2R 2R VR
- 39. R-2R ladder network: VTh for S1 =1 R R R 2R R R 2R R R R VR 2 R R VR 4 2R 2R 2R 2R 2R 2R VR 2R 2R 2R 2R VR
- 40. R-2R ladder network: VTh for S1 =1 R R R 2R R R 2R R R R VR 2 R R VR 4 2R 2R 2R 2R 2R 2R VR 2R 2R 2R 2R VR
- 41. R-2R ladder network: VTh for S1 =1 R R R 2R R R 2R R R R VR 2 R R VR 4 VR VTh = 8 2R 2R 2R 2R 2R 2R VR 2R 2R 2R 2R VR
- 42. R-2R ladder network: VTh for S2 =1 R R R 2R 2R 2R 2R 2R VR
- 43. R-2R ladder network: VTh for S2 =1 R R R 2R 2R 2R 2R 2R VR
- 44. R-2R ladder network: VTh for S2 =1 R R R 2R R 2R 2R VR 2R 2R 2R 2R 2R VR
- 45. R-2R ladder network: VTh for S2 =1 R R R 2R R 2R 2R VR 2R 2R 2R 2R 2R VR
- 46. R-2R ladder network: VTh for S2 =1 R R R 2R R 2R R R VR 2 2R 2R VR 2R 2R 2R 2R 2R VR
- 47. R-2R ladder network: VTh for S2 =1 R R R 2R R 2R R R VR 2 2R 2R VR 2R 2R 2R 2R 2R VR
- 48. R-2R ladder network: VTh for S2 =1 R R R 2R R 2R R R VR 2 VR VTh = 4 2R 2R VR 2R 2R 2R 2R 2R VR
- 49. R-2R ladder network: VTh for S3 =1 R R R 2R 2R 2R 2R 2R VR
- 50. R-2R ladder network: VTh for S3 =1 R R R 2R 2R 2R 2R 2R VR
- 51. R-2R ladder network: VTh for S3 =1 R R R 2R 2R 2R VR 2R 2R 2R 2R VR
- 52. R-2R ladder network: VTh for S3 =1 R R R 2R 2R VTh = 2 VR 2R VR 2R 2R 2R 2R VR
- 53. R-2R ladder network: RTh and VTh R R R 2R 2R 2R 2R 2R RTh VTh S0VR S1VR S2VR S3VR
- 54. R-2R ladder network: RTh and VTh R R R 2R 2R 2R 2R 2R RTh VTh * RTh = R . S0VR S1VR S2VR S3VR
- 55. R-2R ladder network: RTh and VTh R R R 2R 2R 2R 2R 2R RTh VTh * RTh = R . * S0VR S1VR S2VR S3VR
- 56. R-2R ladder network: RTh and VTh R R R 2R 2R 2R 2R 2R RTh VTh * RTh = R . * S0VR S1VR S2VR S3VR * We can use the R-2R ladder network and an Op Amp to make up a DAC → next slide.
- 57. DAC with R-2R ladder Rf Rf RThR R R 2R 2R 2R 2R 2R Vo VoVTh S0VR S1VR S2VR S3VR
- 58. DAC with R-2R ladder Rf Rf RThR R R 2R 2R 2R 2R 2R Vo VoVTh S0VR S1VR S2VR S3VR
- 59. DAC with R-2R ladder Rf Rf RThR R R 2R 2R 2R 2R 2R Vo VoVTh S0VR S1VR S2VR S3VR
- 60. DAC with R-2R ladder Rf Rf RThR R R 2R 2R 2R 2R 2R Vo VoVTh S0VR S1VR S2VR S3VR * 6- to 20-bit DACs based on the R-2R ladder network are commercially available in monolithic form (single chip).
- 61. DAC with R-2R ladder Rf Rf RThR R R 2R 2R 2R 2R 2R Vo VoVTh S0VR S1VR S2VR S3VR * 6- to 20-bit DACs based on the R-2R ladder network are commercially available in monolithic form (single chip). * Bipolar, CMOS, or BiCMOS technology is used for these DACs.
- 62. DAC: Assignment Rf r Vo8R 4R 2R R 8R 4R 2R R S0 VR S1VR S2 VR S3VR S4VR S5 VR S6VR S7 VR Combination of weighted−resistor and R−2R ladder networks * Find the valur of r for the circuit to work as a regular (i.e., binary to analog) DAC. * Find the valur of r for the circuit to work as a BCD to analog DAC.
- 63. DAC: settling time VR VA final value N-bit digital input analog output initial value t ground DN−1 VA D2 D1 D0
- 64. DAC: settling time VR VA final value N-bit digital input analog output initial value t ground * When there is a change in the input binary number, the output VA takes a finite time to settle to the new value. DN−1 VA D2 D1 D0
- 65. DAC: settling time VR VA final value N-bit digital input analog output initial value t ground * When there is a change in the input binary number, the output VA takes a finite time to settle to the new value. * The finite settling time arises because of stray capacitances and switching delays of the semiconductor devices used within the DAC chip. DN−1 VA D2 D1 D0
- 66. DAC: settling time VR VA final value N-bit digital input analog output initial value t ground * When there is a change in the input binary number, the output VA takes a finite time to settle to the new value. * The finite settling time arises because of stray capacitances and switching delays of the semiconductor devices used within the DAC chip. * Example: 500 ns to 0.2 % of full scale. DN−1 VA D2 D1 D0
- 67. ADC: introduction Vmax 111V7 R VR 110 V6 R 101 V5 R VA ′ 100 digital output analog input 4 VR 011 V3 R 010 V2 R ground 3−bit ADC 001 1 VR 000 0 D2 VA D1 D0
- 68. ADC: introduction Vmax 111V7 R VR 110 V6 R 101 V5 R VA ′ 100 digital output analog input 4 VR 011 V3 R 010 V2 R ground 3−bit ADC 001 1 VR 000 0 * If the input VA is in the range V k < VA < V k+1 , the output is the binaryR R number corresponding to the integer k. For example, for VA =V I , the output isA 100. D2 VA D1 D0
- 69. ADC: introduction Vmax 111V7 R VR 110 V6 R 101 V5 R VA ′ 100 digital output analog input 4 VR 011 V3 R 010 V2 R ground 3−bit ADC 001 1 VR 000 0 * If the input VA is in the range V k < VA < V k+1 , the output is the binaryR R number corresponding to the integer k. For example, for VA =V I , the output isA 100. * We may think of each voltage interval (corresponding to 000, 001, etc.) as a “bin.” In the above example, the input voltage V I falls in the 100 bin; therefore,A the output of the ADC would be 100. D2 VA D1 D0
- 70. ADC: introduction Vmax 111V7 R VR 110 V6 R 101 V5 R VA ′ 100 digital output analog input 4 VR 011 V3 R 010 V2 R ground 3−bit ADC 001 1 VR 000 0 * If the input VA is in the range V k < VA < V k+1 , the output is the binaryR R number corresponding to the integer k. For example, for VA =V I , the output isA 100. * We may think of each voltage interval (corresponding to 000, 001, etc.) as a “bin.” In the above example, the input voltage V I falls in the 100 bin; therefore,A the output of the ADC would be 100. * Note that, for an N-bit ADC, there would be 2N bins. D2 VA D1 D0
- 71. ADC: introduction Vmax 111V7 R VR 110 V6 R 101 V5 R VA ′ 100 digital output analog input 4 VR 011 V3 R 010 V2 R ground 3−bit ADC 001 1 VR 000 0 D2 VA D1 D0
- 72. ADC: introduction Vmax 111V7 R VR 110 V6 R 101 V5 R VA ′ 100 digital output analog input 4 VR 011 V3 R 010 V2 R ground 3−bit ADC 001 1 VR 000 0 * The basic idea behind an ADC is simple: D2 VA D1 D0
- 73. ADC: introduction Vmax 111V7 R VR 110 V6 R 101 V5 R VA ′ 100 digital output analog input 4 VR 011 V3 R 010 V2 R ground 3−bit ADC 001 1 VR 000 0 * The basic idea behind an ADC is simple: - Generate reference voltages V 1, V 2 , etc. R R D2 VA D1 D0
- 74. ADC: introduction Vmax 111V7 R VR 110 V6 R 101 V5 R VA ′ 100 digital output analog input 4 VR 011 V3 R 010 V2 R ground 3−bit ADC 001 1 VR 000 0 * The basic idea behind an ADC is simple: - Generate reference voltages V 1, V 2 , etc.R R - Compare the input VA with each of V i to figure out which bin itR belongs to. D2 VA D1 D0
- 75. ADC: introduction Vmax 111V7 R VR 110 V6 R 101 V5 R VA ′ 100 digital output analog input 4 VR 011 V3 R 010 V2 R ground 3−bit ADC 001 1 VR 000 0 * The basic idea behind an ADC is simple: - Generate reference voltages V 1, V 2 , etc.R R - Compare the input VA with each of V i to figure out which bin itR belongs to. - If VA belongs to bin k (i.e., V k < VA < V k+1 ), convert k to theR R binary format. D2 VA D1 D0
- 76. Successive Approximation ADC o C VA Comparator D3 D2 D1 D0 4−bit DAC VDAC
- 77. Successive Approximation ADC o C VA Comparator * Suppose we have a 4-bit DAC. We can use it to perform A-to-D conversion by successively setting the four bits as follows. D3 D2 D1 D0 4−bit DAC VDAC
- 78. Successive Approximation ADC o C VA Comparator * Suppose we have a 4-bit DAC. We can use it to perform A-to-D conversion by successively setting the four bits as follows. - Start with D3 D2 D1 D0 = 0000, I = 3. - Set D[I] =1 (keep other bits unchanged). D3 D2 D1 D0 4−bit DAC VDAC
- 79. Successive Approximation ADC o C VA Comparator * Suppose we have a 4-bit DAC. We can use it to perform A-to-D conversion by successively setting the four bits as follows. - Start with D3 D2 D1 D0 = 0000, I = 3. - Set D[I] =1 (keep other bits unchanged). - If V DAC > V (i.e., C =0), set D[I] =0; else, keep D[I] =1.Ao D3 D2 D1 D0 4−bit DAC VDAC
- 80. Successive Approximation ADC o C VA Comparator * Suppose we have a 4-bit DAC. We can use it to perform A-to-D conversion by successively setting the four bits as follows. - Start with D3 D2 D1 D0 = 0000, I = 3. - Set D[I] =1 (keep other bits unchanged). - If V DAC > V (i.e., C =0), set D[I] =0; else, keep D[I] =1.Ao - I ← I − 1; go to step 1. D3 D2 D1 D0 4−bit DAC VDAC
- 81. Successive Approximation ADC o C VA Comparator * Suppose we have a 4-bit DAC. We can use it to perform A-to-D conversion by successively setting the four bits as follows. - Start with D3 D2 D1 D0 = 0000, I = 3. - Set D[I] =1 (keep other bits unchanged). - If V DAC > V (i.e., C =0), set D[I] =0; else, keep D[I] =1.Ao - I ← I − 1; go to step 1. * At the end of four steps, the digital output is given by D3 D2 D1 D0 . Example → next slide. D3 D2 D1 D0 4−bit DAC VDAC
- 82. Successive Approximation ADC o 30 20 VR o C 10VA (Note: k ∝ VR) step1 2 3 4 5 D4 D3 D2 D1 D0 5−bit DAC VDAC k VDAC 24 k 23 k k VA 16 k D4 = 1 D3 = 1 D2 = 0 D1 = 0 D0 = 0 C = 0 → reset D3 22 k D4 = 1 D3 = 0 D2 = 1 D1 = 1 D0 = 0 C = 1 D4 = 1 D3 = 0 D2 = 1 D1 = 1 D0 = 1 C = 0 → reset D0 20 k D4 = 1 D3 = 0 D2 = 1 D1 = 0 D0 = 0 C = 1 k D4 = 1 D3 = 0 D2 = 0 D1 = 0 D0 = 0 C = 1
- 83. Successive Approximation ADC o 30 20 VR o C 10VA (Note: k ∝ VR) step1 2 3 4 5 * At the end of the 5th step, we know that the input voltage corresponds to 10110. D4 D3 D2 D1 D0 5−bit DAC VDAC k VDAC 24 k 23 k k VA 16 k D4 = 1 D3 = 1 D2 = 0 D1 = 0 D0 = 0 C = 0 → reset D3 22 k D4 = 1 D3 = 0 D2 = 1 D1 = 1 D0 = 0 C = 1 D4 = 1 D3 = 0 D2 = 1 D1 = 1 D0 = 1 C = 0 → reset D0 20 k D4 = 1 D3 = 0 D2 = 1 D1 = 0 D0 = 0 C = 1 k D4 = 1 D3 = 0 D2 = 0 D1 = 0 D0 = 0 C = 1
- 84. Successive Approximation ADC o 30 20 VR o C 10VA (Note: k ∝ VR) step1 2 3 4 5 D4 D3 D2 D1 D0 5−bit DAC VDAC k VDAC 24 k 23 k k VA 16 k D4 = 1 D3 = 1 D2 = 0 D1 = 0 D0 = 0 C = 0 → reset D3 22 k D4 = 1 D3 = 0 D2 = 1 D1 = 1 D0 = 0 C = 1 D4 = 1 D3 = 0 D2 = 1 D1 = 1 D0 = 1 C = 0 → reset D0 20 k D4 = 1 D3 = 0 D2 = 1 D1 = 0 D0 = 0 C = 1 k D4 = 1 D3 = 0 D2 = 0 D1 = 0 D0 = 0 C = 1
- 97. Operation of Successive Approximation ADC (3 Digit)
- 98. 1111 1110 1101 1100 1011 1010 1001 0000 1000 0111 0110 0101 0100 0011 0010 0001 Operation of Successive Approximation ADC (4 Digit) 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
- 99. Successive Approximation ADC Successive Approximation Register VA VDAC o digital output N−bit DAC N−bit SAR Comparator VR Control logic S/H
- 100. Successive Approximation ADC Successive Approximation Register VA VDAC o digital output N−bit DAC * Each step (setting SAR bits, comparison of VA and V DAC ) is performed in one clock cycleo → conversion time is N cycles, irrespective of the input voltage value VA. N−bit SAR Comparator VR Control logic S/H
- 101. Successive Approximation ADC Successive Approximation Register VA VDAC o digital output N−bit DAC * Each step (setting SAR bits, comparison of VA and V DAC ) is performed in one clock cycleo → conversion time is N cycles, irrespective of the input voltage value VA. * S. A. ADCs with built-in or external S/H (sample-and-hold) are available for 8- to 16-bit resolution and conversion times of a few µsec to tens of µsec. N−bit SAR Comparator VR Control logic S/H
- 102. Successive Approximation ADC Successive Approximation Register VA VDAC o digital output N−bit DAC * Each step (setting SAR bits, comparison of VA and V DAC ) is performed in one clock cycleo → conversion time is N cycles, irrespective of the input voltage value VA. * S. A. ADCs with built-in or external S/H (sample-and-hold) are available for 8- to 16-bit resolution and conversion times of a few µsec to tens of µsec. * Useful for medium-speed applications such as speech transmission with PCM. N−bit SAR Comparator VR Control logic S/H
- 103. Successive Approximation ADC Advantages • high accuracy • low power consumption •Easy to use •Low latency-time
- 104. Counting ADC N−bit Counterstart conversion VDAC clock VR Tc o Tc o VA t reset clock digital output Com S/H parator C N−bit DAC VDAC VA
- 105. Counting ADC N−bit Counterstart conversion VDAC clock VR Tc o Tc * The “start conversion” signal clears the counter; counting begins, and V DAC increases witho each clock cycle. o VA t reset clock digital output Com S/H parator C N−bit DAC VDAC VA
- 106. Counting ADC N−bit Counterstart conversion VDAC clock VR Tc o Tc * The “start conversion” signal clears the counter; counting begins, and V DAC increases witho each clock cycle. * When V DAC exceeds VA, C becomes 0, and counting stops.o o VA t reset clock digital output Com S/H parator C N−bit DAC VDAC VA
- 107. Counting ADC N−bit Counterstart conversion VDAC clock VR Tc o Tc * The “start conversion” signal clears the counter; counting begins, and V DAC increases witho each clock cycle. * When V DAC exceeds VA, C becomes 0, and counting stops.o * Simple scheme, but (a) conversion time depends on VA, (b) slow (takes 2N clock cycles in the worst case) → tracking ADC (next slide) o VA t reset clock digital output Com S/H parator C N−bit DAC VDAC VA
- 108. “ The Important thing about a problem is not its solution , but the strength we gain in finding the solution ” - Anonymous Thanks Everybody