Dx33746752

Raman Bondare, Rajesh Langote / International Journal of Engineering Research and
Applications (IJERA) ISSN: 2248-9622 www.ijera.com
Vol. 3, Issue 3, May-Jun 2013, pp.746-752
746 | P a g e
Comparative Approach to Conventional and Fast Locking Digital
Phase Locked Loops
*Raman Bondare, **Rajesh Langote
*Shri Ramdeobaba College of Engineering & Management, India
**Priyadarshani College of Engineering, India
Abstract
A digital phase-locked loop (DPLL) is
designed using 180 nm CMOS process and a 3.3
V power supply. It operates in the frequency
range 200 MHz–1 GHz. The DPLL operation
includes two stages: (i) a novel coarse-tuning
stage based on a flash algorithm, and (ii) a fine-
tuning stage similar to conventional DPLLs. The
flash portion of the DPLL is made up of
frequency comparators, an encoder and a
decoder which drives a multiple charge pump
(CP)/low pass filter (LPF) combination. Design
considerations of the flash DPLL circuit
components as well as implementation using
Tanner design tools are presented. Spectra
simulations were also performed and
demonstrated a significant improvement in the
lock time of the flash DPLL as compared to the
conventional DPLL.
Keywords — PFD, MCP, LPF, VCO, CP, FC.
I. INTRODUCTION
Phase-locked loops (PLLs) are
commonplace in applications like wireless
transceivers, global positioning systems, clock
generators and so on. A major characteristic of the
PLL is the lock time; it is the time the PLL takes to
adapt and settle after a sudden change of the input
signal frequency.
Conventional PLLs inherently take long
time to lock since the output frequency undergoes
the entire iterative process before reaching natural
convergence; this renders these PLLs unfit for
contemporary high-speed, high throughput
applications needed for information technology.
Examples of conventional digital phase-locked loops
(DPLLs) using 0.18 mm CMOS process are given in
[1, 2]. The DPLL in [1] is a 55 MHz–1.43 GHz one
with a lock time of 840 ns at 1 GHz and 1.22 ms at
1.43 GHz. The DPLL in [2] is a 1 GHz one with a
lock time of 643 ns at that frequency. These two
examples represent the state-of-the-art of
conventional DPLLs using 0.18 mm CMOS process.
Fast locking is required for fast frequency
hopping among data bursts in high-speed digital
communications [3]. PLLs with low-power
constraints demand that they be turned off during
inactivity, but then require that they lock quickly
when turned back on. Fast locking is therefore a
necessity for spread-spectrum communications,
cellular phones, clock/data recovery circuits and so
on. In fast- locking DPLLs, phase locking is speeded
up via a fast-start mechanism that accounts for most
of the frequency change, whereas the output
frequency undergoes the above- mentioned natural
iterative convergence process, which characterises
conventional DPLLs, over the remaining very small
frequency range.
Although the literature on PLLs contains
several thousands of designs and research papers,
the literature on fast-locking PLLs is very limited
(several tens) because of the more recent great
demand. Research papers include some well-known
techniques for PLL fast locking, for example (i)
using a non-linear phase detector (PD) to obtain fast
locking and good jitter damping thus overcoming
the problem of requiring a high natural frequency
for fast locking and a low one for good jitter
damping, (ii) a digital hybrid PLL frequency
synthesizer which provides coarse tuning with a
loop filter, fine tuning with a D/A converter (DAC)
to control the voltage-controlled oscillator (VCO)
and a frequency control word applied to a
programmable counter and look-up table and (iii) a
dual-slope PFD based on two loops, one for coarse
tuning and one for fine tuning.
There is also a number of US patents in the
literature such as (i) US patent # 6,380,810
containing a speed-up circuit amplifying a
differential voltage coupled to a filter capacitor
creating a coarse-tune VCO voltage via rapid
charging and discharging [5], (ii) US patent #
6,566,966 where the VCO employs a controller and
a DAC [6], (iii) US patent # 6,624,705 which
presents a PLL with reduced cycle slip during
acquisition; it includes a charge pump (CP) with
selectable output current ranges, (iv) US patent #
6,624,707 employing gain control via a feedback
circuit to adjust the loop gain at any specific tuning
voltage and consequently the current gain of the
PFD and (v) US Patent # 6,940,356 for a DPLL
employing multiple charge pumps (MCP) .
There are a number of industrial
corporations that produce fast-locking PLLs, for
example, Analog Devices Inc. that uses a timer in
the fast-lock mode to determine the time of the wide
bandwidth, True Circuits Inc. that uses a Lock
Now! technology and National Semiconductor Inc.
that adaptively multiplies the charge-pump current.

747 | P a g e
The above literature reveals that fast-locking
DPLLs fall under the following categories: (i)
techniques based on a mathematical algorithm to
achieve fast convergence, (ii) techniques based on
non-linear characteristics of the CP to change the
convergence rate, (iii) techniques based on a
feedback mechanism associated with the PD or the
CP and iv) techniques based on using current-mode
techniques in lieu of voltage-mode techniques.
Section II describes the flash DPLL theory
of operation. This is a novel technique whereby the
word ‘flash’ is borrowed from ‘flash A/D
converters’ to signify very fast achievement of a
thermometer code that approximates the value of the
analogue input voltage via an array of parallel
voltage comparators; the net result is a very fast
ADC conversion time of one clock cycle. In the
proposed flash DPLL, an analogous array of
frequency comparators is used to produce, after a
very small delay, a thermometer code that
approximates the value of applied input frequency.
The thermometer code thus continuously detects any
positive or negative hops in the input frequency, and
consequently causes the DPLL to undergo a fast-
start mechanism that will ultimately shorten the lock
time; a new contribution to the literature on fast-
locking DPLLs. It will be useful for applications that
require very fast DPLL locking, for example,
spread-spectrum communications, cellular phones,
clock/data recovery circuits, information technology
and so on.
Section III describes the design of the flash
DPLL employing both the conventional and fast-
locking hardware. Some of the components are
standard circuits, whereas others are only used in
this paper. Section IV describes the implementation
and simulation of both the flash DPLL and its
conventional counterpart. Section V provides
conclusions of the work.
II. BLOCK DIAGRAM OF THE FLASH DPLL
The original block diagram of the novel
flash fast-locking DPLL is shown in Fig. 1. The
circuit quickly and simultaneously compares the
input frequency with many equispaced fixed
frequencies covering the entire anticipated frequency
range of operation. Now, frequency comparison
results will be represented by a thermometer code to
be applied to a DAC, the output of which will
control the VCO, thus ending the coarse-tuning
stage. This stage is followed by a fine-tuning stage,
where locking will take place like a conventional
DPLL. It should be noted that during the fine-tuning
stage the switch is closed, which may give the
impression that the VCO has two inputs rather than
one. However, the VCO block contains a provision
such that when the LPF output is applied to the
VCO, the DAC output will be automatically
switched out of the VCO, thus there is effectively
only one input to the VCO. Since the fine-tuning
stage covers a much narrower frequency range,
while the fast-locking hardware is disabled, the
transient response of this stage is minimal. By
adding the convergence times of both coarse-tuning
and fine-tuning stages, the resulting DPLL lock time
will be much smaller than that had the coarse-tuning
stage not existed.
This hypothesis fills an important gap in the
literature since it is the counterpart of the concept
given in [9], which achieves fast locking via an
algorithm similar to the one used in successive-
approximation ADCs. However, the much faster
flash algorithm, as applied to DPLLs, is expected to
result in a significant reduction in lock time at the
expense of additional hardware.
Figure 1 Original block diagram of the novel flash
DPLL[16]
Although the concept of this design seems
logical, it was found after building and testing it that,
with the switching sequence and circuitry that were
attempted, the CP was not able to react fast enough
to the coarse-tuning stage as expected. It was then
easier to remove the DAC and replace the single CP
with a MCP activated by a decoder which selects the
CP suitable for a particular frequency jump (hop) at
the input. The modified block diagram is given in
Fig. 2, which falls under both categories (i) and (ii)
mentioned above in Section I.
The flash DPLL operates by monitoring
any changes in the input signal frequency (Fin)
every, say 20 ns, using an array of, say eight,
frequency comparators with reference frequencies
(Fref), ranging from 250 MHz to 2 GHz. Once a
change in Fin is detected during any 20 ns cycle, an
additional 20 ns cycle is needed to accurately
estimate the new input frequency, since the
frequency hop takes place at any time during the
first 20 ns cycle. Thus 40 ns are needed to coarsely
estimate the new input frequency. The thermometer
code, at the output of the frequency comparator
array, is applied to a priority encoder which outputs
a 3-bit binary code to a decoder, which in turn
selects one-out-of-eight charge pumps (CPs)/low
pass filters (LPFs). The LPF output voltage is then
inputted into the VCO which produces the closest
frequency to the new input frequency; this marks the
end of the coarse-tuning stage. The selected CP/LPF
will stay in use until a new Fin has been detected.

748 | P a g e
The remaining time to lock the DPLL is regarded as
the fine-tuning stage, where locking will take place
like a conventional DPLL while the frequency
comparators, encoder and decoder are not affecting
circuit operation. Since coarse tuning sets the VCO
frequency to the closest possible to Fin, the fine-
tuning time is thus cut down tremendously, as
compared to the conventional DPLL thus resulting
in a much faster lock time.
Figure 2 Modified block diagram of the novel flash
DPLL
III.DESIGN OF THE FLASH DPLL
The circuit components of the flash DPLL of Fig.
2 are given below:
A. Phase-frequency detector
The block diagram of the phase-frequency
detector (PFD) is given in [8].The outputs UP and
DN (Down) depend on the frequency and lead/lag
relationship between the input Fin and Fvco (VCO
output frequency). When the loop is locked, the UP
and DN remain low.
B. Voltage-controlled oscillator
A current-starved VCO is built, which is
basically composed of an odd number of inverter
stages, as given in [8]. For proper operation, M4
(connected to VDD) and M5 (connected to the VCO
input Vcntrl) have to operate in the saturation
region. The VCO oscillation frequency is given by
[8].
Where Ctot is the total load capacitance at
the drain of inverters, and t1 and t2 are the charge
and discharge times. A five-stage VCO was used
because it requires less input voltage than that of a
seven- or nine-stage VCO. Table 1 shows the
required voltages needed to produce a specific
frequency. Two inverters were used at the VCO
output to give sharp waveform edges.
In order to test the VCO, a ramp was used
at the input to allow oscillations to begin. The ramp
was set up to 1.36 V. The resulting Fvco was 2 GHz
which agrees with Table 1.
C. MCP and LPFs
1) Single CP and LPF: A single CP is shown in Fig.
3. A precise current mirror is used to remove
instability and ripple in the control voltage. The
output control voltage Vcntrl will increase/decrease
depending on whether the UP/DN pulse occurs. The
CP starting voltage is an important design factor
since it helps in decreasing the lock time of the
DPLL. This voltage can be controlled by modifying
the aspect ratio (W/L) of N1 and P2. The LPF is
shown in Fig. 3.
TABLE 1
VCO FREQUENCY AGAINST VOLTAGE (VCNTRL)
Frequency Voltage (Vcntrl)
250 MHz 865 mV
500 MHz 1.038 V
750 MHz 1.14 V
1 GHz 1.2 V
1.25 GHz 1.25 V
1.5 GHz 1.28 V
1.75 GHz 1.32 V
2 GHz 1.36 V
Figure 3 Single CP and LPF
2) MCP and LPFs:
The MCP design, shown in Fig.4, is made
up of eight individual CPs; each CP has a different
starting control voltage. The output bits of the
decoder control the MCP. When a single CP is
selected, only its pertinent switches close, thus
allowing the UP/DN pulses from the PFD to be input
to the CP. Table 2 display the required aspect ratios
to produce the starting voltage levels of the CPs; the
output of the selected CP (Table 2) has an initial
voltage level which is slightly larger than the
required voltage level for each specific frequency
(Table 1). The LPF output voltage Vcntrl is thus
input into the VCO with a slight overshoot to speed
up the DPLL. Each CP has its own LPF although all
LPFs are identical; this prevents the capacitor from

749 | P a g e
keeping the charge of the previously used CP thus
each capacitor starts fresh when a new input
frequency is detected.
D. Frequency comparators
The frequency comparator is the most
essential component of the FLASH DPLL. It is what
determines which CP to use, thus allowing a faster
lock time. The frequency comparator array is shown
in Fig. 5. Depending on the input frequency Fin and
the reference frequencies Fref, the output of each
individual comparator will be either high ‘1’ or low
‘0’. The block diagram of Fig. 7 has one common
input Fin and seven outputs (A1–A7); it also shows
that each individual frequency comparator has three
inputs (Fin, Fref and Reset). The ‘Reset’ input
receives a pulse every 20 ns to reset the entire array
of frequency comparators so that it can begin a new
comparison every 20 ns. The outputs of all
comparators constitute the ‘thermometer code’ to be
inputted into the priority encoder.
Figure 4 MCP schematic
In this design, a novel frequency
comparator [10] was attempted; it uses ring counters
to determine whether the input signal is slower or
faster than the reference signal. The advantage of
this type is that it always gives correct comparison
results regardless of the phase shift between the
input and reference signals. To account for the cases
when the comparator cannot decide during an
arbitrarily allotted time frame (we selected 20 ns),
we added a Time-Out flag to the output of the
frequency comparator. The idea is that ‘Time-Out =
1’ means that both Fin and Fref are too close to each
other, thus it is a good approximation to assume that
Fin >Fref for that particular comparator even if this
is not true and thus the comparator’s decision would
be ‘1’; this small error during the coarse-tuning stage
would be accounted for anyhow during the fine-
tuning stage of the flash DPLL. The frequency
comparator block of Fig. 7 is made up of seven of
such comparator type. Thus, the lowest frequency
comparator (#7) in Fig. 7 compares Fin with Fref7 of
500MHz, while the frequency comparator above it
(#6) compares Fin with Fref6 of 750MHz and so
forth.
Figure 5 Block diagram of an array of frequency
comparators
E. Priority encoder
The purpose of the encoder is to translate
the output signals of the frequency comparator array
into a 3-bit binary code that will get inputted into the
decoder. To generate a 3-bit binary code at the
output, that is, b1–b3 (b1 being the LSB) from an
input array A1–A7 (A1 being the LSB), the design
procedure used is outlined in [9]. The circuit was
implemented using AND, OR, INVERT logic.
TABLE 2
STARTING CP VOLTAGE CONTROL OUTPUT
PER ASPECT RATIO
Charge
pump
Aspect ratio Voltage
(Vcntrl),
VP2 (W/L) N1(W/L)
1 11/0.18 10.5/0.18 1.04
2 11/0.18 8.5/0.18 1.20
3 11/0.18 8/0.18 1.26
4 11/0.18 7.75/0.18 1.29
5 11/0.18 7.25/0.18 1.35
6 11/0.18 7/0.18 1.39
7 11/0.18 6.65/0.18 1.44
8 11/0.18 6.25/0.18 1.50

750 | P a g e
It should be noted that, in our present design using
only seven frequency comparators, the eight rows of
Table 3 (top to bottom) correspond to the following
input frequency ranges, respectively: (<500 MHz),
(500–750 MHz), (750 MHz–1 GHz), (1–1.25 GHz),
(1.25–1.5 GHz), (1.5–1.75 GHz), (1.75–2 GHz) and
(>2 GHz).
F. Decoder
The three to eight decoder selects one-out-
of-eight CPs. When all three inputs are ‘0’, this
makes B0 = 1, and when all inputs are ‘1’, this
makes B7 = 1. Bits B0–B7 energizes CPs # 1–8,
respectively. The circuits were implemented using
AND, OR, INVERT logic.
IV. IMPLEMENTATION AND
SIMULATIONS OF THE FLASH DPLL
To prove that the flash DPLL locks much
faster than the conventional DPLL, both are
compared.
A. Conventional DPLL
Fig. 6 shows part of the flash DPLL,
namely the conventional DPLL. It is composed of a
PFD, CP (CP#1 was used), LPF and VCO. This
excludes the flash portion, namely frequency
comparator, encoder, decoder and MCP.
Many examples were performed in the
frequency range 300 MHz–2 GHz. To determine the
lock time, the voltage (Vcntrl) from the CP was
monitored and the input frequency (Fin) was
compared with the output frequency (Fvco). The
DPLL is considered to be locked. The phase shift
between Fvco and Fin becomes zero or constant.
Example simulations for the frequency range 300
MHz–1.8 GHz are shown in Fig. 7.
Figure 6 Conventional DPLL simulation schematic
Figure 7 Conventional DPLL 300 MHz–1.8 GHz
Hop (zoomed to view waveforms at locking)
B. The flash DPLL
Fig. 8 shows the flash DPLL schematic
used for simulations. Since we do not know when
the input frequency hop takes place during any 20 ns
cycle, we actually need two 20 ns cycles, that is, 40
ns; the first 20 ns cycle is needed to detect a change
in Fin, whereas the second 20 ns cycle is used to
decide which frequency is larger. If Fin changes
again during the second 20 ns cycle, this change will
be resolved, that is, a decision as to which frequency
Fin (new) or Fref is larger, during the next 20 ns
cycle.
Figure 8 Flash DPLL simulation schematic
To perform simulations, the frequency
comparator array was removed and replaced with
Vpulse signals that are manually programmed to
output the exact signal levels per frequency hop, as
that of the frequency comparator. The reason for
such replacement is the slow processing speed the
spectra software. To simulate the frequency
comparator array, it took disproportionately long
times, compared to the time taken by an individual
frequency comparator. Since the circuitry of the
frequency comparator array is so complicated and
involves a great amount of parallel processing, with
the software doing thousands of calculations, this
made it difficult to obtain sufficient data, taking
hours and days to run just a small percentage of the
full simulation. Thus the array of frequency
comparators was replaced by a block which merely
exhibits 40 ns delay then places the thermometer
code, corresponding to the new input frequency
under consideration (after the frequency hop), at the
input of the priority encoder. This method of
simulation provides a reasonably good estimate of
the DPLL lock times for different input frequency
hops.
Many examples were performed in the
frequency range 300 MHz–2 GHz. Example
simulations for the positive frequency hop of 300
MHz–1.8 GHz are shown in Fig. 9; it clearly shows
an input frequency hop taking place at 200 ns, which

751 | P a g e
is followed by a conventional change of Vcntrl
during the above-mentioned 40 ns delay. At about
240 ns, Vcntrl jumps steeply when the new CP is
selected, thus marking the end of the coarse-tuning
stage and the beginning of the fine-tuning stage; the
later stage ends with the DPLL locking at 297 ns,
that is, a lock time of 97 ns.
Figure 9 Flash DPLL 1.8 GHz–300 MHz Hop (hop
took place at 200 ns and Tlock = 119 ns)
TABLE 3
LOCK-TIME COMPARISON FOR FLASH AND
CONVENTIONAL
DPLLS FOR DIFFERENT FREQUENCY HOPS
Frequency hop
Fast-locking
DPLL, ns
Conventional
DPLL, ns
300 MHz–800
MHz
92 150
800 MHz–1 GHz 103 217
1 GHz–1.8 GHz 97 312
C. Comparison tables
Table 3 provides a summary of simulation
results. It compares the fast-locking DPLL against
the conventional DPLL; it also compares all lock
times for different values of input frequency hops.
Thus, the significance of this paper’s contribution is
that it not only represents a significant advancement
since the publication of the conventional DPLLs in
[1, 2], but also represents an advanced technique
within the new hot area of fast-locking DPLLs.
V. CONCLUSIONS
A novel fast-locking DPLL was designed to
improve the lock time over that of the conventional
DPLL. The fast-locking DPLL employs a flash
algorithm similar to the one employed in flash A/D
converters, thus expecting fast response at the
expense of increased hardware. The flash DPLL
operation employs two stages: (i) a novel coarse-
tuning stage comprising an array of frequency
comparators, encoder, decoder, MCPs, LPFs and
VCO; during this stage the DPLL output frequency
gets as close as possible to the input final frequency
in a very short time, and (ii) a fine-tuning stage
comprising a PFD, CP, LPF and the VCO; this stage
resembles the operation of conventional DPLLs. The
frequency comparator array as well as the
MCP/LPFs constitute the extra hardware penalty
because of using the flash fast-locking technique,
thus there is a speed against hardware tradeoff.
Design considerations for various circuit
components were discussed and some pertinent
testing results were provided. The entire
conventional DPLL was easy to simulate. However,
the entire flash DPLL was only possible to simulate
after replacing the frequency comparator array with
a block that exhibits time delay and finally produces
a thermometer code representing the new input
frequency (after the frequency hop). The flash DPLL
was verified to operate in frequency range 300
MHz–1.8 GHz. Table 3 demonstrates that there is a
significant improvement in the lock time by using
the flash DPLL as opposed to the conventional
DPLL.
Faster lock times of the flash fast-locking
DPLL can be achieved by including a larger array of
frequency comparators composed of 16 or 32
comparators; this will result in a finer coarse-tuning
stage and consequently a faster fine-tuning stage. It
is thus expected that all lock times will be below the
100 ns mark in the above mentioned frequency
range.
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752 | P a g e
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