The document discusses the Apple A5 chip, which implements the ARM Cortex-A9 processor. It includes an overview of the Cortex-A9 architecture, addressing modes, CPU modes, instruction sets, and key components of the A5 system-on-chip including the snoop control unit, accelerator coherency port, AMBA 3 AXI bus, and generic interrupt controller. The Cortex-A9 adheres to the ARMv7 architecture and includes SIMD and floating-point instructions.

1. Apple Processor
A5 Chip

2. Cortex A9
• Cortex has three variants:
- A series (application)
-R series (real time)
-M series (microcontroller)
• A5 is an implementation of Cortex A9 MP core.
• PoP(Package on Package)
• SoC (System on a Chip)
• Cortex A9 adheres to ARMv7.

5. ARMv7
• Acorn RISC Machine
• Benefits Of RISC.
• Additional ARM Features
 instructions that combine a shift with an arithmetic or
logical operation
 auto-increment and auto-decrement addressing modes
to optimize program loops
 Load and Store Multiple instructions to maximize data
throughput
 conditional execution of almost all instructions to
maximize execution throughput.

6. Block Diagram

7. Addressing modes
• Load/Store instruction: base and offset
• Memory Addressing modes
-Offset
-Pre-Indexed
-Post-Indexed
• Offset forms:
– Immediate
– Register
– Scaled Register

8. CPU Modes
User mode
Privileged mode
Exception mode(FIQ, IRQ, Supervisor, Abort,
Undefined, Monitor)
System mode
Why they needed?

11. Vector Table

13. APSR CPSR and SPSR

15. Instruction Extensions
• ARM instruction set – default 32 bit
instruction set present in ARM arch.
• Thumb – 16 bit instruction set used as subset
of ARM instr. set to reduce code density at
cost of performance.
• Thumb 2 – 32 bit instruction set with better
performance than thumb.
• Jazelle – Java byte code execution extension
and required part of arch. Since ARMv6

17. NEON/VFPv3
• Provide support for the ARM v7 SIMD and
Vector Floating-Point v3 (VFPv3) instruction
sets.
• The SIMD vector operations include:
– Addition
– subtraction
– Multiplication

18. VFPv3 D16 architecture

19. Cortex A9 MP core
• SCU(snoop control unit)
• ACP(Accelerator Coherency Port)
• AMBA 3 AXI(Advanced Microcontroller Bus
Architecture 3 with Advanced eXtensible
Interface)
• GIC(Generic Interrupt Controller)

20. Snoop Control Unit
• The SCU connects one to four Cortex-A9
processors to the memory system through the
AXI interfaces.
• maintain data cache coherency
• initiate L2 AXI memory accesses
• arbitrate between Cortex-A9 processors
requesting L2 accesses
• manage ACP accesses.

21. Accelerator Coherency Port
• 64-bit port that can be connected to non-
cached AXI master peripherals
• Data Coherency between non cached master
peripheral and CPU is maintained by this port

22. Advanced Microcontroller Bus
Architecture
• Connection and management of components
on SoC.
• The third generation of AMBA protocol
defines AXI
• AXI improves the performance and used in
high clock frequency systems.
• Improves Scalability.

23. GIC(Generic Interrupt Controller)
• registers for managing interrupt sources,
interrupt behavior, and interrupt routing to
one or more processors.
• One interrupt interface per Cortex-A9
processor.
• GIC architecture splits logically into a
Distributor block and one or more CPU
Interface blocks
• It works on interrupts ID.

24. GIC provides support for:
•the ARM architecture Security Extensions
•enabling, disabling, and generating processor
interrupts from hardware (peripheral) interrupt
sources
•generating software interrupts
•interrupt masking and prioritization
•uniprocessor and multiprocessor
environments.

25. Why ARM?

26. Why ARM?

27. Drawbacks of ARM
• All drawbacks of RISC over CISC.
• ARM does not support Windows
• Why not in desktops?

28. What's next?
Apple A6 implements some functionality of
Cortex –A15 that has ARMv8 as
Microarchitecture.
But First Custom Core Processor that is better
than A5!(Obviously) by Apple Inc.