2. ARM History
• First ARM was developed by Acorn
Computers Limited, Cambridge between
1983 & 1985
– First commercial RISC Processor
• In 1990, the company named Advanced
RISC Machines Limited was formed
• Later it was renamed as ARM Limited
• ARM has been licensed to many
semiconductor manufacturers like:
– National Semiconductor
– Philips
– Atmel,etc
5. RISC Design Philosophy
• Is based on simple but powerful
instructions that execute within a single
cycle at a high clock speed.
6. 4 Major Design Rules
1) Instructions :
• Mostly single cycled instructions, except
for few.
• The Compiler or programmer synthesizes
complicated instructions.
• Having fixed length which helps in
pipelining.
7. Cnt’d
• 2) Pipelining:
• The processing of instructions is broken
down into smaller units that can be
executed in parallel by pipelines.
• Maximizes throughput.
8. Cnt’d
• 3) Registers :
• Large general-purpose register set.
• Any register can contain either data or an
address.
• Registers act as the fast local memory
store for all data processing operations.
9. Cnt’d
• 4) Load-store architecture :
• Register Intensive processing
• Separate load and store instructions
• Maximizes multiple access of reg-banks
Minimizes multiple memory accesses.
10. ARM Architectural Features
• ARM core use a RISC architecture
• 32-bit processor core (32-bit
instructions)
• Reduced Gate Count design, Suitable
for small, low power, high performance
implementations
• Features High Code density
• Smaller area on die
11. • Incorporates 3 levels of on chip
hardware debug technology
A) JTAG debug port/interface
B) Embedded Trace Module (ETM)
C) Real Time Monitor
12. • Simple addressing modes
• Uniform and fixed length instruction set
to simplify instruction decode
• Load & Store Multiple Instructions to
maximize data throughput
• Conditional execution of all
instructions to maximize the execution
throughput
13. Cont’d
• 37, 32-bit internal registers (16
available)
• Cached (depending on the
implementation)
• Von Neuman-type bus structure
(ARM7), Harvard (ARM9)
• 8 / 16 / 32 -bit data types
• 7 modes of operation for arm core
14. Processor Modes
• The processor mode determines which
registers are active and the access
rights to the cpsr(flag) register itself.
• A privileged mode allows full read-write
access to the cpsr
• A nonprivileged mode only allows read
access to the control field in the cpsr,
but still allows full read-write access to
the condition flags
15. Seven processor modes
• Six privileged modes
Abort, fast interrupt request, interrupt
request, supervisor,system, and undefined
• One nonprivileged mode
user
16. • Abort mode : When there is a failed
attempt to access memory
• Fast interrupt request and interrupt
request modes : Correspond to the two
interrupt levels
• Supervisor mode : The processor is in
after reset (when power is applied) and
is generally the mode that an operating
system kernel operates in
• System mode :Special version of user
mode that allows full read-write access
to the cpsr
17. • Undefined mode :
When the processor encounters an
instruction that is undefined or not
supported by the implementation
• User mode:
Used for programs and applications
18. Pipelined Architecture:
• ARM 7(3-Stage) :
Instruction Fetch (F),
Instruction Decode (D),
Execute (E)
• ARM9 (5-Stage) :
Instruction Fetch (F),
Instruction Decode (D),
Execute (D),
Data Memory access (M),
Register Write (W)
• ARM11(8-Stage) :
Two Fetch Stages ,
A decode Stage,
An Issue Stage,
Four Stages for the
execution Pipeline
19. • As the pipeline length increases, the
amount of work done at each stage is
reduced, which allows the processor
attain a higher operating frequency
• This in turn increases the performance
• This also increases the latency
20. ARM is not pure RISC.
Its instruction SET Differs from pure RISC
as:
• Variable cycle execution for certain
instructions
• Inline barrel shifter leading to more
complex instructions
• Thumb 16 bit instructions set
• Condition execution
• Enhanced (DSP) instructions
• Jazelle Support (70 % Java Byte Codes)
21. ARM Core Data Flow
Model (Von Neumann implementation)
• An ARM core can be viewed as
functional units connected by data
buses
• The data may be an instruction or a
data item
