Benchmark Processors- VAX 8600,MC68040,SPARC and Superscalar RISC
VAX 8600, MC 68040,
SUN MICROSYSTEM SPARC,
IIEST Shibpur, M.Tech CST 2014-16
VAX : Virtual Address Extension (32-bit extension of the older 16-bit early versions)
Manufacturer: Digital Equipment Corporation (DEC).
First Model: VAX-11/780
VAX is a family of popular and influential computers implementing VAX Instruction Set
The VAX 8600, ("Venus“,Oct 1984), had increased performance(4.2 times VAX-11/785),
I/O capacity, and included macro-pipelining and ECL (emitter coupled logic).
Cycle Time of VAX 8600 CPU: 80 ns(12.5 MHz)
Implements CISC architecture with micro programmed control.
300 instructions with 20 different addressing modes.
Two functional units for concurrent execution of instruction of integer and floating point
Pipeline is built with six stages.
The instruction unit prefetches and decodes and handles branching operations.
A transistor look aside buffer (TLB) is used in memory for fast generation of the physical
address from the virtual address
Fig: The VAX
memory & I/O,
Virtual addr to
floating inst. ,
SBI- Synchronous Backplane Interconnect
• The MC68040 is a 0.8 μm HCMOS microprocessor containing more than 1.2 million
• It's implemented over 100 instructions using 16 general-purpose register.
• 4kb of data cache and 4kb of instruction cache with separate memory management
unit (MMU's) supported by a address translation cache.
• Support 18 addressing modes, integer unit is organized in six stages of instruction
pipeline, floating point consist of 3 stages.
• Separate instruction and data buses are provided both addressing and data buses are of
• The complete memory unit is provided with a virtual demand paged operating system.
*ATC- Address Translation The CPU of MC 68040
• SPARC ("scalable processor architecture")
• Uses RISC instruction set architecture (ISA)
• Developed by Sun Microsystems
• Designed for optimizing compilers and easy pipelined hardware implementations.
• Exceptionally high execution rates(MIPS) and short time-to-market development
• 3 major revisions to the SPARC architecture
- SPARC-V7, 32bit, 1986
- SPARC-V8, 32bit, 1990
- SPARC-V9, 64bit, 1993
ISA contains 69 basic instructions. 8 Global Registers
Runs procedure 32 bit Register
Ins, OUTs, Locals
Shared among procedures Locally addressable by
The calling procedure passes parameters to the called procedure via its Outs registers which are the Ins
Register of the called procedure.
Window of the
A window invalid mask is used to indicate which
window is invalid .
The trap base register servers as a pointer to a trap
Most important feature :-
Overlapped Register Window introduced by Berkeley RISC architecture.
It divides the register file into small groups ,called windows and each procedure uses one
Adjacent windows can pass parameters and hence called overlapped.
8 overlapping windows (64
local registers ,64 overlapped
reg.) and 8 global registers .
Total = 136 reg. each 32 bit
Fig: Cypress CY7C601 SPARC processor
Superscalar processor is a multiple issue processor .
RISC – Reduced Instructions Set Computer.
RISC CPUs like Intel i960CA were the first microprocessors to use the superscalar concept.
It has 5 stage pipeline : fetch, dispatch, issue, execute and complete.
It has 3 execution units:
a) simple arithmetic and logic ( includes branch address computation)
b) complex arithmetic (multiply and divide), and
c) memory data access (includes a simple ALU)
All program memory and data memory busses are 16 bits wide.
The processor fetches at most one instruction but may issue up to 3 instructions at a
time for execution.
It has three functional units – branch processor, fixed-point unit and floating-point unit.
These three can operate in parallel .
* The fixed point processor uses non privileged instructions
VAX 8600 MC 68040 SPARC SUPERSCALAR
CISC CISC RISC RISC
20 address mode
Plus 100 instr.
18 address mode
69 basic instr.
Few address mode
6 stage pipeline 6 stage pipeline- integer
unit, 3 stage - floating
4 stage pipeline 5 stage pipeline
16 GPRS 16GPRS (8 for addr., 8
40 to 520 GPRS 16GPRS
TLB used for 1st
time- 64 entries
TLB size- 64 entries Software Managed
Reorder Buffer- 32
1.2 Million Transistors .
Faster processor than
VAX, uses High Speed
Multi issue processor.
A short cycle time and
a low cycles-per-instruction