The document discusses a team presentation on MIPS implementation and pipelining. The team includes Mehedi Hasan, Sabiha Sultana, and Mohammed Refeya. It defines MIPS, describes MIPS calculations and features. It also discusses MIPS implementation including logic circuits, processor datapath, organizations, and single-cycle datapath/control. Finally, it covers pipelining and the stages of pipelining including instruction fetch, decode, execution, memory access, and write back.
1. Team Name : Pentium 4
Name ID
Mehedi Hasan 18203058
Sabiha Sultana 18203038
Mohammed Refeya 18203108
Presantation Topic:
MIPS Implementation & pipelining
3. It is an older, obsolete measure of
a computer's speed and power.
MIPS measures roughly the number of
machine instructions that a computer
can execute in one second.
What is MIPS?
Million instructions per second
5. MIPS specifies instruction execution rate
MIPS does not take into account the
capabilities of the instructions
Thus, it is impossible to compare computers
with different ISA using MIPS.
MIPS is not constant, even on a single
machine, depends on the application.
6. Logic circuits use two different values of a physical quantity, usually
voltage, to represent the bulean values true (or 1) and false (or 0).
Logic circuits can have inputs and they have one or more outputs
that are, at least partially, dependent on their inputs
a logic circuit can have multiple outputs.
There are two basic types of logic circuitry: combinational circuitry
and state circuitry
1. Combinational circuitry behaves like a simple function. The
output of combinational circuitry depends only on the current values
of its input.
2. State circuitry behaves more like an object method. The output
of state circuitry does not just depend on its inputs — it also
depends on the past history of its inputs. In other words, the
circuitry has memory.
7.
8. A processor's datapath is conceptually organized into two parts:
•State elements hold information about the state of the processor
during the current clock cycle. All registers are state elements.
•Combinational logic determines the state of the processor for the
next clock cycle. The ALU is combinational logic.
9. There are four major processor organizations:
Single-cycle organization- It is characterized by the fact
that each instruction is executed in a single clock cycle. It is not a
realistic implementation — it requires two separate memories: one
for data and one for instructions. Also, the clock cycle has to be
made quite long in order for all of the signals generated in a cycle to
reach stable values.
Multicycle organization- This organization uses multiple
clock cycles for executing each instruction. Each cycle does only a
small part of the work required so the cycles are much shorter. Much
of the circuitry is the same as the single-cycle implementation.
10. Pipelined organization- Like the multicycle organization,
the pipelined organization uses multiple clock cycles for executing
each instruction. By adding more state components for passing data
and control signals between cycles, the pipelined organization turns
the circuitry into an assembly line. After the first cycle of one
instruction has completed you can start the execution of another
instruction, while the first moves to its next cycle. Several
instructions can be in different phases of execution at the same
time.
Register renaming organization - Register
renaming is an extension of the pipelining idea. It deals with the
data dependence problem for a pipeline — the fact that
instructions in the pipeline produce data needed by other
instructions in the pipeline
11. There are two basic types of logic components:
combinational components and state
components.
A combinational component behaves like a simple
function. Its outputs depend only on the current
values of its inputs.
A state component behaves more like an object
method. Its output also depends on the past
history of its inputs.
12. • IF – Instruction Fetch
• ID – Instruction Decode
• EX – Execution
• MEM – Memory Access
• WB – Write Back
Pipelining