The document provides a comprehensive overview of convolutional codes, including their introduction, encoder design, representations, and advantages in error correction for digital communications. It discusses the structure of convolutional encoders, such as state diagrams and trellis diagrams, with examples illustrating the encoded sequences and parameters. Convolutional codes improve data capacity in communication channels and are effectively decoded using the Viterbi algorithm.

1. A nutshell on Convolutional Codes (representations)
PREPARED BY,
ALKA DILEEP(14304002)
SWARA G.I.K(14304026)
M-TECH ECE
PONDICHERRY UNIVERSITY

2. OUTLINE
▪ An introduction to convolutional codes
 An introduction to convolutional encoder
▪ Convolutional codes representations and explanation with
examples
Generator representation
State diagram
Tree diagram
Trellis diagram
 Advantages of Convolutional codes
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3. FORWARD ERROR CORRECTION CODE
There are four important forward error correction codes that find
applications in digital transmission. They are :
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Block Parity
Hamming Code
Interleaved Code
Convolutional Code

4. CONVOLUTIONAL CODES : AN INTRODUCTION
 Convolutional codes are introduced in 1955 by Elias.
 Convolution coding is a popular error-correcting coding method
used in digital communications. A message is convoluted, and then
transmitted into a noisy channel.
 This convolution operation encodes some redundant information
into the transmitted signal, thereby improving the data capacity of
the channel.
 The Viterbi algorithm is a popular method used to decode
convolutionally coded messages.
 The block codes can be applied only for the block of data whereas
convolution coding can be applied to a continuous data stream as
well as to blocks of data.
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5. CONVOLUTIONAL ENCODER
▪ Convolutional encoder is a finite state machine (FSM), processing
information bits in a serial manner.
▪ Convolutional encoding of data is accomplished using a shift register and
associated combinatorial logic that performs modulo-two addition.
▪ A shift register is merely a chain of flip-flops wherein the output of the
nth flip-flop is tied to the input of the (n+1)th flip flop.
▪ Every time the active edge of the clock occurs, the input to the flip-flop is
clocked through to the output, and thus the data are shifted over one stage.
▪ In convolutional code the block of n code bits generated by the encoder in
a particular time instant depends not only on the block of k message bits
within that time instant but also on the block of data bits within a previous
span of N-1 time instants (N>1).
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6.  A convolutional code with constraint length N consists of an N-stage
shift register (SR) and ν modulo-2 adders.
Fig (a): A convolutional Encoder
 Fig (a) shows a coder for the case N=3 and ν=2. The message bits are
applied at the input of the shift register (SR). The coded digit stream is
obtained at the commutator output. The commutator samples the ν modulo-2
adders in a sequence, once during each input-bit interval.
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7. Example: Assume that the input digits are 1010. Find the coded
sequence output for Fig(a).
Initially, the Shift Registers s1=s2=s3=0.
When the first message bit 1 enters the SR, s1= 1, s2 = s3=0.
Then ν1=1, ν2=1 and the coder output is 11.
When the second message bit 0 enters the SR, s1=0, s2=1, s3=0.
Then ν1=1 and ν2=0 and the coder output is 10.
When the third message bit 1 enters the SR, s1=1, s2=0 and s3=1
Then ν1=0 and ν2=0 and the coder output is 00.
When the fourth message bit 0 enters the SR, s1=0, s2=1 and s3=0
Then ν1=1 and ν2=0 and the coder output is 10.
The coded Output Sequence is : 11100010
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8. PARAMETERS OF A CONVOLUTIONAL ENCODER
Convolutional codes are commonly specified by three parameters: (n,k,m)
n = number of output bits
k = number of input bits
m = number of memory registers
Code Rate: The quantity k/n is called as code rate. It is a measure of the
efficiency of the code.
Constraint Length: The quantity L(or K) is called the constraint length of the
code. It represents the number of bits in the encoder memory that affect the
generation of the n output bits. It is defined by
Constraint Length, L = k (m-1)
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9. ENCODER REPRESENTATIONS
The encoder can be represented in several different but equivalent ways. They are
1. Generator Representation
2. Tree Diagram Representation
3. State Diagram Representation
4. Trellis Diagram Representation
(A) Generator Representation
Generator representation shows the hardware connection of the shift register
taps to the modulo-2 adders. A generator vector represents the position of the taps
for an output. A “1” represents a connection and a “0” represents no connection.
For example, the two generator vectors for the encoder in Fig(a) are g1 =
[111] and g2 = [101], where the subscripts 1 and 2 denote the corresponding output
terminals.
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10. (B) State Diagram Representation
 In the state diagram, the state information of the encoder is shown in the
circles. Each new input information bit causes a transition from one state to
another.
Contents of the rightmost (K-1) shift register stages define the states of the
encoder. So, the encoder in Fig(b) has four states. The transition of an
encoder from one state to another, as caused by input bits, is depicted in the
state diagram.
The path information between the states, denoted as x/c, represents input
information bit x and output encoded bits c.
 It is customary to begin convolutional encoding from the all zero state.
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11. Example: Consider the half rate encoder in the following figure:
The present state values are the possible 2 bit combinations for both 0
and 1 input. The output AB is obtained from the expressions in the Fig
(b). Then, the next state values are calculated by right shifting the input
and present state values together by 1 bit position.
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Fig (b) Half Rate
Encoder

12. Truth Table for the encoder in Fig(b)
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INPUT PRESENT STATE OUTPUT NEXT STATE
0 00 00 00
0 01 11 00
0 10 01 01
0 11 10 01
1 00 11 10
1 01 00 10
1 10 10 11
1 11 01 11

13. From the truth table the state diagram is constructed as
follows:
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Fig (c) State Diagram

14. Interpretations from state diagram
Let 00 State a ; 01 State b; 10 State c; 11 State d;
(1) State a goes to State a when the input is 0 and the output is 00
(2) State a goes to State b when the input is 1 and the output is 11
(3) State b goes to State c when the input is 0 and the output is 10
(4) State b goes to State d when the input is 1 and the output is 01
(5) State c goes to State a when the input is 0 and the output is 11
(6) State c goes to State b when the input is 1 and the output is 00
(7) State d goes to State c when the input is 0 and the output is 01
(8) State d goes to State d when the input is 1 and the output is 10
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15. (C) Tree Diagram Representations
The tree diagram representation shows all possible information and
encoded sequences for the convolutional encoder.
 In the tree diagram, a solid line represents input information bit 0 and a
dashed line represents input information bit 1.
The corresponding output encoded bits are shown on the branches of
the tree.
 An input information sequence defines a specific path through the tree
diagram from left to right.
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Fig (d) Tree Diagram

17. (D) Trellis diagram Representation
The trellis diagram is basically a redrawing of the state diagram. It
shows all possible state transitions at each time step.
The trellis diagram is drawn by lining up all the possible states (2L) in
the vertical axis. Then we connect each state to the next state by the
allowable codeword’s for that state.
There are only two choices possible at each state. These are determined
by the arrival of either a 0 or a 1 bit.
The arrows show the input bit and the output bits are shown in
parentheses.
 The arrows going upwards represent a 0 bit and going downwards
represent a 1 bit.
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18. Steps to construct trellis diagram
 It starts from scratch (all 0’s in the SR, i.e., state a) and makes
transitions corresponding to each input data digit.
These transitions are denoted by a solid line for the next data digit 0
and by a dashed line for the next data digit 1.
 Thus when the first input digit is 0, the encoder output is 00 (solid
line)
When the input digit is 1, the encoder output is 11 (dashed line).
 We continue this way for the second input digit and so on as depicted
in Fig (e) that follows.
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19. Trellis diagram for the state diagram mentioned before
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Fig(e) Trellis diagram

20. AN EXAMPLE IN DETAIL:(2,1,4) CONVOLUTIONAL ENCODER
The (2,1,4) code in Fig(f) has a constraint length of 3 and a code rate of
1/2.The shaded registers below hold these bits. The unshaded register
holds the incoming bit. This means that 3 bits or 8 different
combinations of these bits can be present in these memory registers.
Fig(f) : (2,1,4) CONVOLUTIONAL 20
ENCODER

21. Let us give an input sequence (1011) to the encoder in Fig(f).
Then the coded output sequence will be obtained as follows:
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22. Truth Table of (2,1,4) encoder for the sequence (1011)
INPUT BIT PRESENT ENCODER
STATE
OUTPUT BIT NEXT ENCODER
STATE
1 000 11 100
0 100 11 010
1 010 01 101
1 101 11 110
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(A) State Diagram Representation for the above truth
table
Steps involved to construct state diagram:
 Conventionally we start from state 000.
 The arrival of a 1 bit outputs 11 and state transition occurs to 100.
 The arrival of next 0 bit outputs 11 and state transition occurs to 010.
 The arrival of next 1 bit outputs 01 and state transition occurs to 101.
 The arrival of last 1 bit outputs 11 and state transition occurs to 110.
So now we have the coded output sequence as 11 11 01 11.

24. State diagram for (1011)
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Fig (g): State diagram of (2,1,4) encoder for
sequence 1011

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(B) Tree Diagram Representation
Steps involved in constructing tree diagram for input sequence 1011:
The first branch indicates the arrival of a 0 or a 1 bit. The starting state is
assumed to be 000.If 0 is received we go upwards and if 1 is received we go
downwards. The first two bits shows the output bits and the number inside
the parenthesis is the output state.
At branch 1 we go down. The output is 11 and we are in state 111.
Now we get a 0 bit and we go upward. The output bits are 11 and the state is
now 011.
The next incoming bit is 1,we go downwards and get an output of 01 and now
the output state is 101.
The next incoming bit is 1 so we again go downwards and get the output bit
as 11.

26. Fig(h): Tree diagram of (2,1,4) encoder for 26
sequence 1011

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(C)Trellis Diagram Representation
Steps involved in constructing the Trellis diagram:
We start from 000.
 In the trellis diagram the incoming bits are shown on top.
 For input 1 bit, the output is 11 and it goes down to state 100.
 For the next o bit , the output is 11 and it goes upward to the state 010.
 For the next 1 bit, the output is 01 and it goes downward to the state
101.
 For the last 1 bit, the output is 11 and it goes downward to the state
110.

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Fig(i): Trellis diagram of (2,1,4) encoder for
sequence 1011

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ADVANTAGES OF CONVOLUTIONAL CODES
Convolution coding is a popular error-correcting coding method used
in digital communications.
The convolution operation encodes some redundant information into
the transmitted signal, thereby improving the data capacity of the
channel.
Convolution Encoding with Viterbi decoding is a powerful FEC
technique that is particularly suited to a channel in which the
transmitted signal is corrupted mainly by AWGN.
It is simple and has good performance with low implementation cost.

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