IOSR Journal of Computer Engineering (IOSR-JCE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of computer engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in computer technology. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
VLSI ARCHITECTURE FOR NANO WIRE BASED ADVANCED ENCRYPTION STANDARD (AES) WITH...VLSICS Design
Advanced Encryption Standard (AES) Algorithm has been extensively applied in the present financial
applications. Sub-channel attacks are one of the main problems occurred n the AES Algorithm.
Asynchronous AES Architecture is one of the leading solutions of the sub-channel attacks due to its natural
properties. The AES architecture with the enhanced mix column to be proposed with reduced number of
transistor counts.. Then, the Verilog A modeling is used to evaluate the performance of the proposed AES
Architecture. Finally, the VLSI Implementations of the AES Processor is implemented with CMOS
technology 0.25 µm. By using the net list generations, the proposed AES Architecture is analyzed regarding
the VLSI design environment. The simulation results of the proposed structure are performed with the
minimum number of transistor counts as well as power utilizations. Moreover, the proposed CMOS
technology based AES Algorithm is integrated into the backend based chip technology.
Arm recognition encryption by using aes algorithmeSAT Journals
Abstract To provide the security of the Military confidential data we use encryption algorithm which take over reward of superior encryption algorithm. The proposed implementation using encryption algorithm was implemented on ARM 7 to encrypt and decrypt the confidential data on data storage devices such as SD card or Pen drive. The main objective of proposed implementation is to provide protection for storage devices. The ARM and encryption algorithm protect the data accessibility, reliability and privacy successfully. Since (AES) Advanced Encryption Standard algorithm is widely used in an embedded system or fixed organization. These AES algorithms are used for proper designs in defense for security. Keywords: Plain text, Cipher text, Data security, AES, Embedded System.ARM, storage device.
Novel Adaptive Hold Logic Circuit for the Multiplier using Add Round Key and ...IJMTST Journal
Digital multipliers are among the most critical arithmetic functional units in many applications, such as the Fourier transform, discrete cosine transforms, and digital filtering. The through put of these applications depends on multipliers, if the multipliers are too slow, the performance of entire circuits will be reduced. The negative bias temperature instability effect occurs when a PMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of a PMOS transistor and reducing the multiplier speed. Similarly, positive bias temperature instability occurs when an NMOS transistor is under positive bias. Both effects degrade the speed of the transistor and in the long term, the system may be fail due to timing violations. Therefore, it is required to design reliable high-performance multipliers. In this paper, we implement an aging aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide the higher throughput through the variable latency and can adjust the adaptive hold logic (AHL) circuit to lessen performance degradation that is due to the aging effect. The proposed design can be applied to the column bypass multiplier.
An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithmijsrd.com
A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S -box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.
Hardware implementation of aes encryption and decryption for low area & power...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
VLSI ARCHITECTURE FOR NANO WIRE BASED ADVANCED ENCRYPTION STANDARD (AES) WITH...VLSICS Design
Advanced Encryption Standard (AES) Algorithm has been extensively applied in the present financial
applications. Sub-channel attacks are one of the main problems occurred n the AES Algorithm.
Asynchronous AES Architecture is one of the leading solutions of the sub-channel attacks due to its natural
properties. The AES architecture with the enhanced mix column to be proposed with reduced number of
transistor counts.. Then, the Verilog A modeling is used to evaluate the performance of the proposed AES
Architecture. Finally, the VLSI Implementations of the AES Processor is implemented with CMOS
technology 0.25 µm. By using the net list generations, the proposed AES Architecture is analyzed regarding
the VLSI design environment. The simulation results of the proposed structure are performed with the
minimum number of transistor counts as well as power utilizations. Moreover, the proposed CMOS
technology based AES Algorithm is integrated into the backend based chip technology.
Arm recognition encryption by using aes algorithmeSAT Journals
Abstract To provide the security of the Military confidential data we use encryption algorithm which take over reward of superior encryption algorithm. The proposed implementation using encryption algorithm was implemented on ARM 7 to encrypt and decrypt the confidential data on data storage devices such as SD card or Pen drive. The main objective of proposed implementation is to provide protection for storage devices. The ARM and encryption algorithm protect the data accessibility, reliability and privacy successfully. Since (AES) Advanced Encryption Standard algorithm is widely used in an embedded system or fixed organization. These AES algorithms are used for proper designs in defense for security. Keywords: Plain text, Cipher text, Data security, AES, Embedded System.ARM, storage device.
Novel Adaptive Hold Logic Circuit for the Multiplier using Add Round Key and ...IJMTST Journal
Digital multipliers are among the most critical arithmetic functional units in many applications, such as the Fourier transform, discrete cosine transforms, and digital filtering. The through put of these applications depends on multipliers, if the multipliers are too slow, the performance of entire circuits will be reduced. The negative bias temperature instability effect occurs when a PMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of a PMOS transistor and reducing the multiplier speed. Similarly, positive bias temperature instability occurs when an NMOS transistor is under positive bias. Both effects degrade the speed of the transistor and in the long term, the system may be fail due to timing violations. Therefore, it is required to design reliable high-performance multipliers. In this paper, we implement an aging aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide the higher throughput through the variable latency and can adjust the adaptive hold logic (AHL) circuit to lessen performance degradation that is due to the aging effect. The proposed design can be applied to the column bypass multiplier.
An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithmijsrd.com
A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S -box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.
Hardware implementation of aes encryption and decryption for low area & power...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
hardware implementation of aes encryption and decryption for low area & low p...Kumar Goud
Abstract-An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilinx tool.
High Speed VLSI Architecture for AES-Galois/Counter ModeIJERA Editor
Galois/Counter Mode of Operation (GCM) is a block cipher mode operation used to provide encryption and
authentication using universal Hashing based on multiplication over binary Galois/Finite Field.GCM can be
implemented on both hardware and software effectively and efficiently. GCM supports pipelined and
parallelized implementations to have minimal computational latency in order to be useful at high data rates.
However need for continual performance improvement is still presented due to continuous increase in network
bandwidth and inefficiency of existing parallelization methods. This paper presents use of modified parallel
GHASH module and modified key Expansion module to improve overall efficiency. GCM architecture is
modeled in Verilog HDL and Simulated in Xilinx ISE. ASIC implementation is done on 130 nm CMOS
technology. Test case 4 of NIST submission for Galois/Counter Mode (GCM) is also verified.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Modified Blowfish algorithm analysis using derivation casesjournalBEEI
This study analyzed and enhanced the modified Blowfish algorithm (MBA) encryption. The modification retained the original structure, process and the use of two S-boxes in the MBA but presented two derivation processes in the f-function which was originally placed to prevent symmetry. The derivation case’s performance was analyzed using avalanche effect and time efficiency. After comparing the first and second derivation process presented in the MBA, the second derivation further improved the avalanche effect by 5.47%, thus improving security. The performance also showed that the second modification is faster by 39.48% in encryption time, and 38.34% faster in decryption time. The first derivation case in the modified Blowfish was slower in time because of the difference in the placement of the shift rotation. The key generation time was found to be independent of the input size while the encryption and decryption time was found to be directly proportional to file size. With this, the second modification is considered to be better.
An OpenCL Method of Parallel Sorting Algorithms for GPU ArchitectureWaqas Tariq
In this paper, we present a comparative performance analysis of different parallel sorting algorithms: Bitonic sort and Parallel Radix Sort. In order to study the interaction between the algorithms and architecture, we implemented both the algorithms in OpenCL and compared its performance with Quick Sort algorithm, the fastest algorithm. In our simulation, we have used Intel Core2Duo CPU 2.67GHz and NVidia Quadro FX 3800 as graphical processing unit.
International Refereed Journal of Engineering and Science (IRJES)irjes
International Refereed Journal of Engineering and Science (IRJES) is a leading international journal for publication of new ideas, the state of the art research results and fundamental advances in all aspects of Engineering and Science. IRJES is a open access, peer reviewed international journal with a primary objective to provide the academic community and industry for the submission of half of original research and applications
SQUASHED JPEG IMAGE COMPRESSION VIA SPARSE MATRIXijcsit
To store and transmit digital images in least memory space and bandwidth image compression is needed. Image compression refers to the process of minimizing the image size by removing redundant data bits in a manner that quality of an image should not be degrade. Hence image compression reduces quantity of the image size without reducing its quality. In this paper it is being attempted to enhance the basic JPEG compression by reducing image size. The proposed technique is about amendment of the conventional run length coding for JPEG (Joint Photographic Experts Group) image compression by using the concept of sparse matrix. In this algorithm, the redundant data has been completely eliminated and hence leaving the quality of an image unaltered. The JPEG standard document specifies three steps: Discrete cosine transform, Quantization followed by Entropy coding. The proposed work aims at the enhancement of the third step which is Entropy coding.
Fully Homomorphic Encryption Using Low Power MultiplierIJERA Editor
The design of a power and area efficient high speed 768 000-bit multiplier based on Fast Fourier Transform (FFT) multiplication for fully homomorphic encryption operations. Memory based in-place architecture is presented for the FFT processor that performs 64 000-point finite-field FFT operations using a radix-16 computing unit and 16 dual-port SRAMs. By adopting a special prime as the base of the finite field, the radix-16 calculations are simplified to requiring only additions and shift operations. A two-stage carry-look-ahead scheme is employed to resolve carries and obtain the multiplication result. The multiplier design is validated by comparing its results with the GNU Multiple Precision (GMP) arithmetic library. The proposed design has been synthesized using 90-nm process technology with an estimated die area of 45.3 mm2. At 200 MHz, the large-number multiplier offers roughly twice the performance of a previous implementation on an NVIDIA C2050 graphics processor unit and is 29 times faster than the Xeon X5650 CPU, while at the same time consuming a modest 0.97 W.
A New hybrid method in watermarking using DCT and AESIJERD Editor
In this paper I'm trying to make a combination between the encryption by using one of the most
powerful algorithm called Advanced Encryption Standard (AES) to encrypt a secret message another word logo
and then embed it in the digital image in frequency domain by using the Discrete Cosine Transform (DCT) in
low frequency to increase the robustness and then applying some attacks to check it.
The concept of motion image based wireless monitoring and control system, the main requirements from the M2M communities and related encryption method of the wireless system are described. Section I is the introduction of M2M system, section II is the concept for the scrambling of motion image based video signals with transcendental number that is iterated over Fibonacci prime number sequence, with video time stamp and user pass phrase ...
Encryption and Compression of Audio-Video Data Using Enhanced AES and J-Bit A...ijsrd.com
AES is considered a good encryption algorithm in terms of providing security to a network in passing information (data) in form of audio, string, and video and in any other form. However it yields a low throughput resulting in slowness and increasing energy dispensation of server or an application. The Enhanced AES algorithm is proposed in this paper which works by using sequence counters and provides improved throughput as compare to conventional AES algorithm. The J-Bit Encoding is being a compression algorithm in lossless category which doesn't decrease the quality but reduce the size of data to some extent. It has been observed that the proposed encryption algorithm integrated to J-Bit Encoding algorithm will provide the effective security measures as well as increased throughput as a parameter and less bandwidth usage as the actual size of data shall not be sent along the network.
Inverted Index Based Multi-Keyword Public-key Searchable Encryption with Stro...Mateus S. H. Cruz
Presentation given at the SWIM seminar (University of Tsukuba) about the paper "Inverted Index Based Multi-Keyword Public-key Searchable Encryption with Strong Privacy Guarantee"*.
This presentation is based on the uploader's understanding of the paper and may contain inaccurate interpretations.
A summary of the paper is available at: https://mshcruz.wordpress.com/2016/10/24/summary-inverted-index-based-multi-keyword-public-key-searchable-encryption-with-strong-privacy-guarantee/
*Wang et al.: "Inverted Index Based Multi-Keyword Public-key Searchable Encryption with Strong Privacy Guarantee". INFOCOM 2015.
This is a project dealing with securing images over a network.
Image is a delicate piece of information shared between clients across the world.Cryptography plays a huge role during secure connections.Applying simple Gaussian elimination to achieve highly secured image encryption decryption technique is a interesting challenge.
hardware implementation of aes encryption and decryption for low area & low p...Kumar Goud
Abstract-An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilinx tool.
High Speed VLSI Architecture for AES-Galois/Counter ModeIJERA Editor
Galois/Counter Mode of Operation (GCM) is a block cipher mode operation used to provide encryption and
authentication using universal Hashing based on multiplication over binary Galois/Finite Field.GCM can be
implemented on both hardware and software effectively and efficiently. GCM supports pipelined and
parallelized implementations to have minimal computational latency in order to be useful at high data rates.
However need for continual performance improvement is still presented due to continuous increase in network
bandwidth and inefficiency of existing parallelization methods. This paper presents use of modified parallel
GHASH module and modified key Expansion module to improve overall efficiency. GCM architecture is
modeled in Verilog HDL and Simulated in Xilinx ISE. ASIC implementation is done on 130 nm CMOS
technology. Test case 4 of NIST submission for Galois/Counter Mode (GCM) is also verified.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Modified Blowfish algorithm analysis using derivation casesjournalBEEI
This study analyzed and enhanced the modified Blowfish algorithm (MBA) encryption. The modification retained the original structure, process and the use of two S-boxes in the MBA but presented two derivation processes in the f-function which was originally placed to prevent symmetry. The derivation case’s performance was analyzed using avalanche effect and time efficiency. After comparing the first and second derivation process presented in the MBA, the second derivation further improved the avalanche effect by 5.47%, thus improving security. The performance also showed that the second modification is faster by 39.48% in encryption time, and 38.34% faster in decryption time. The first derivation case in the modified Blowfish was slower in time because of the difference in the placement of the shift rotation. The key generation time was found to be independent of the input size while the encryption and decryption time was found to be directly proportional to file size. With this, the second modification is considered to be better.
An OpenCL Method of Parallel Sorting Algorithms for GPU ArchitectureWaqas Tariq
In this paper, we present a comparative performance analysis of different parallel sorting algorithms: Bitonic sort and Parallel Radix Sort. In order to study the interaction between the algorithms and architecture, we implemented both the algorithms in OpenCL and compared its performance with Quick Sort algorithm, the fastest algorithm. In our simulation, we have used Intel Core2Duo CPU 2.67GHz and NVidia Quadro FX 3800 as graphical processing unit.
International Refereed Journal of Engineering and Science (IRJES)irjes
International Refereed Journal of Engineering and Science (IRJES) is a leading international journal for publication of new ideas, the state of the art research results and fundamental advances in all aspects of Engineering and Science. IRJES is a open access, peer reviewed international journal with a primary objective to provide the academic community and industry for the submission of half of original research and applications
SQUASHED JPEG IMAGE COMPRESSION VIA SPARSE MATRIXijcsit
To store and transmit digital images in least memory space and bandwidth image compression is needed. Image compression refers to the process of minimizing the image size by removing redundant data bits in a manner that quality of an image should not be degrade. Hence image compression reduces quantity of the image size without reducing its quality. In this paper it is being attempted to enhance the basic JPEG compression by reducing image size. The proposed technique is about amendment of the conventional run length coding for JPEG (Joint Photographic Experts Group) image compression by using the concept of sparse matrix. In this algorithm, the redundant data has been completely eliminated and hence leaving the quality of an image unaltered. The JPEG standard document specifies three steps: Discrete cosine transform, Quantization followed by Entropy coding. The proposed work aims at the enhancement of the third step which is Entropy coding.
Fully Homomorphic Encryption Using Low Power MultiplierIJERA Editor
The design of a power and area efficient high speed 768 000-bit multiplier based on Fast Fourier Transform (FFT) multiplication for fully homomorphic encryption operations. Memory based in-place architecture is presented for the FFT processor that performs 64 000-point finite-field FFT operations using a radix-16 computing unit and 16 dual-port SRAMs. By adopting a special prime as the base of the finite field, the radix-16 calculations are simplified to requiring only additions and shift operations. A two-stage carry-look-ahead scheme is employed to resolve carries and obtain the multiplication result. The multiplier design is validated by comparing its results with the GNU Multiple Precision (GMP) arithmetic library. The proposed design has been synthesized using 90-nm process technology with an estimated die area of 45.3 mm2. At 200 MHz, the large-number multiplier offers roughly twice the performance of a previous implementation on an NVIDIA C2050 graphics processor unit and is 29 times faster than the Xeon X5650 CPU, while at the same time consuming a modest 0.97 W.
A New hybrid method in watermarking using DCT and AESIJERD Editor
In this paper I'm trying to make a combination between the encryption by using one of the most
powerful algorithm called Advanced Encryption Standard (AES) to encrypt a secret message another word logo
and then embed it in the digital image in frequency domain by using the Discrete Cosine Transform (DCT) in
low frequency to increase the robustness and then applying some attacks to check it.
The concept of motion image based wireless monitoring and control system, the main requirements from the M2M communities and related encryption method of the wireless system are described. Section I is the introduction of M2M system, section II is the concept for the scrambling of motion image based video signals with transcendental number that is iterated over Fibonacci prime number sequence, with video time stamp and user pass phrase ...
Encryption and Compression of Audio-Video Data Using Enhanced AES and J-Bit A...ijsrd.com
AES is considered a good encryption algorithm in terms of providing security to a network in passing information (data) in form of audio, string, and video and in any other form. However it yields a low throughput resulting in slowness and increasing energy dispensation of server or an application. The Enhanced AES algorithm is proposed in this paper which works by using sequence counters and provides improved throughput as compare to conventional AES algorithm. The J-Bit Encoding is being a compression algorithm in lossless category which doesn't decrease the quality but reduce the size of data to some extent. It has been observed that the proposed encryption algorithm integrated to J-Bit Encoding algorithm will provide the effective security measures as well as increased throughput as a parameter and less bandwidth usage as the actual size of data shall not be sent along the network.
Inverted Index Based Multi-Keyword Public-key Searchable Encryption with Stro...Mateus S. H. Cruz
Presentation given at the SWIM seminar (University of Tsukuba) about the paper "Inverted Index Based Multi-Keyword Public-key Searchable Encryption with Strong Privacy Guarantee"*.
This presentation is based on the uploader's understanding of the paper and may contain inaccurate interpretations.
A summary of the paper is available at: https://mshcruz.wordpress.com/2016/10/24/summary-inverted-index-based-multi-keyword-public-key-searchable-encryption-with-strong-privacy-guarantee/
*Wang et al.: "Inverted Index Based Multi-Keyword Public-key Searchable Encryption with Strong Privacy Guarantee". INFOCOM 2015.
This is a project dealing with securing images over a network.
Image is a delicate piece of information shared between clients across the world.Cryptography plays a huge role during secure connections.Applying simple Gaussian elimination to achieve highly secured image encryption decryption technique is a interesting challenge.
Fast, Private and Verifiable: Server-aided Approximate Similarity Computation...Mateus S. H. Cruz
Presentation given at the SWIM seminar (University of Tsukuba) about the paper "Fast, Private and Verifiable: Server-aided Approximate Similarity Computation over Large-Scale Datasets"*.
This presentation is based on the uploader's understanding of the paper and may contain inaccurate interpretations.
A summary of the paper is available at: https://mshcruz.wordpress.com/2016/08/05/summary-fast-private-and-verifiable-server-aided-approximate-similarity-computation-over-large-scale-datasets/
*Qiu et al.: "Fast, Private and Verifiable: Server-aided Approximate Similarity Computation over Large-Scale Datasets". SCC 2016.
ENKI: Access Control for Encrypted Query ProcessingMateus S. H. Cruz
Presentation given at the SWIM Seminar (University of Tsukuba) about ENKI*.
This presentation is based on the uploader's understanding of the paper and may contain inaccurate interpretations.
A summary of the paper is available at: https://mshcruz.wordpress.com/2016/07/11/summary-enki/
*Hang et al.: "ENKI: Access Control for Encrypted Query Processing". SIGMOD 2015.
Fuzzy Keyword Search over Encrypted Data in Cloud ComputingMateus S. H. Cruz
Presentation about the paper "Fuzzy Keyword Search over Encrypted Data in Cloud Computing"*.
This presentation is based on the uploader's understanding of the paper and may contain inaccurate interpretations.
A summary of the paper is available at: https://mshcruz.wordpress.com/2016/08/16/summary-fuzzy-keyword-search-over-encrypted-data-in-cloud-computing/
*Li et al.: "Fuzzy Keyword Search over Encrypted Data in Cloud Computing". INFOCOM 2010.
Privacy-Preserving Multi-Keyword Fuzzy Search over Encrypted Data in the CloudMateus S. H. Cruz
Presentation given at the SWIM seminar (University of Tsukuba) about the paper "Privacy-Preserving Multi-Keyword Fuzzy Search over Encrypted Data in the Cloud"*.
This presentation is based on the uploader's understanding of the paper and may contain inaccurate interpretations.
A summary of the paper is available at: https://mshcruz.wordpress.com/2016/08/19/summary-privacy-preserving-multi-keyword-fuzzy-search-over-encrypted-data-in-the-cloud/
*Wang et al.: "Privacy-Preserving Multi-Keyword Fuzzy Search over Encrypted Data in the Cloud". INFOCOM 2014.
A design of a fast parallel pipelined implementation of aes advanced encrypti...ijcsit
The Advanced Encryption Standard (AES) algorithm is a symmetric block cipher which operates on a
sequence of blocks each consists of 128, 192 or 256 bits. Moreover, the cipher key for the AES algorithm is
a sequence of 128, 192 or 256 bits. AES algorithm has many sources of parallelism. In this paper, a design
of parallel AES on the multiprocessor platform is presented. While most of the previous designs either use
pipelined parallelization or take advantage of the Mix_Column parallelization, our design is based on
combining pipelining of rounds and parallelization of Mix_Column and Add_Round_Key transformations.
This model is divided into two levels: the first is pipelining different rounds, while the second is through
parallelization of both the Add_Round_Key and the Mix_Column transformations. Previous work proposed
for pipelining AES algorithm was based on using nine stages, while, we propose the use of eleven stages in
order to exploit the sources of parallelism in both initial and final round. This enhances the system
performance compared to previous designs. Using two-levels of parallelization benefits from the highly
independency of Add_Round_Key and Mix_Column/ Inv_Mix_Colum transformations. The analysis shows
that the parallel implementation of the AES achieves a better performance. The analysis shows that using
pipeline increases significantly the degree of improvement for both encryption and decryption by
approximately 95%. Moreover, parallelizing Add_Round_Key and Mix_Column/ Inv_Mix_Column
transformations increases the degree of improvement by approximately 98%. This leads to the conclusion
that the proposed design is scalable and is suitable for real-time applications
VLSI Architecture for Nano Wire Based Advanced Encryption Standard (AES) with...VLSICS Design
Advanced Encryption Standard (AES) Algorithm has been extensively applied in the present financial applications. Sub-channel attacks are one of the main problems occurred n the AES Algorithm. Asynchronous AES Architecture is one of the leading solutions of the sub-channel attacks due to its natural properties. The AES architecture with the enhanced mix column to be proposed with reduced number of transistor counts.. Then, the Verilog A modeling is used to evaluate the performance of the proposed AES Architecture. Finally, the VLSI Implementations of the AES Processor is implemented with CMOS technology 0.25 µm. By using the net list generations, the proposed AES Architecture is analyzed regarding the VLSI design environment. The simulation results of the proposed structure are performed with the minimum number of transistor counts as well as power utilizations. Moreover, the proposed CMOS technology based AES Algorithm is integrated into the backend based chip technology.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
Design and Analysis of Parallel AES Encryption and Decryption Algorithm for M...iosrjce
This paper presents information on AES Encryption and Decryption for multi processors. In this
paper AES algorithm is used. The AES algorithm is a round based algorithm. The round based algorithm is
used to provide security to the information. In AES algorithm there are different types of keys, they are 128,192
and 256 bits. These bits are used to encrypt and decrypt the information. In this paper 128bits are used. In this
paper the main functional blocks are key generation, encryption and decryption. In order produce a new key sub
byte, rotate word, round constant and add round key operations are used. In order to convert plain text to
cipher message the sub bytes, shift rows, mix column and add round key operations are used. By doing these
operations the cipher information is obtained. This cipher will be given to the decryption and it is the total
reverse process of encryption. After completion of reverse process the outcome is original information.
The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data also called Rijndael. The algorithm described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data. Hardware-based cryptography is used for authentication of users and of software updates and installations. Software implementations can generally not be used for this, as the cryptographic keys are stored in the PC memory during execution, and are vulnerable to malicious codes. Hardware-based encryption products can also vary in the level of protection they provide against brute force rewind attacks, Offline parallel attacks, or other cryptanalysis attacks. The algorithm was implemented in FPGA due to its flexibility and reconfiguration capability. A reconfigurable device is very convenient for a cryptography algorithm since it allows cheap and quick alterations. The implementation of pipelined cryptography hardware was used to improve performance in order to achieve higher throughput and greater parallelism. The AES hardware was implemented in three modules contains of the encryption, the decryption and the key expansion module.
High throughput FPGA Implementation of Advanced Encryption Standard AlgorithmTELKOMNIKA JOURNAL
The growth of computer systems and electronic communications and transactions has meant that the need for effective security and reliability of data communication, processing and storage is more important than ever. In this context, cryptography is a high priority research area in engineering. The Advanced Encryption Standard (AES) is a symmetric-key criptographic algorithm for protecting sensitive information and is one of the most widely secure and used algorithm today. High-throughput, low power and compactness have always been topic of interest for implementing this type of algorithm. In this paper, we are interested on the development of high throughput architecture and implementation of AES algorithm, using the least amount of hardware possible. We have adopted a pipeline approach in order to reduce the critical path and achieve competitive performances in terms of throughput and efficiency. This approach is effectively tested on the AES S-Box substitution. The latter is a complex transformation and the key point to improve architecture performances. Considering the high delay and hardware required for this transformation, we proposed 7-stage pipelined S-box by using composite field in order to deal with the critical path and the occupied area resources. In addition, efficient AES key expansion architecture suitable for our proposed pipelined AES is presented. The implementation had been successfully done on Virtex-5 XC5VLX85 and Virtex-6 XC6VLX75T Field Programmable Gate Array (FPGA) devices using Xilinx ISE v14.7. Our AES design achieved a data encryption rate of 108.69 Gbps and used only 6361 slices ressource. Compared to the best previous work, this implementation improves data throughput by 5.6% and reduces the used slices to 77.69%.
Design and Implementation A different Architectures of mixcolumn in FPGAVLSICS Design
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An Optimized Parallel Mixcolumn and Subbytes design in Lightweight Advanced E...ijceronline
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Pipelining Architecture of AES Encryption and Key Generation with Search Base...VLSICS Design
A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has the advantage of increased throughput and offers better security. Search based S-box architecture has been proposed in this paper to reduce the constraint in the hardware resources. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm. Moreover the key schedule algorithm of the AES encryption is pipelined to get the speedup.
Pipelining Architecture of AES Encryption and Key Generation with Search Base...VLSICS Design
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A New Approach for Video Encryption Based on Modified AES Algorithm
1. IOSR Journal of Computer Engineering (IOSR-JCE)
e-ISSN: 2278-0661,p-ISSN: 2278-8727, Volume 17, Issue 3, Ver. VI (May – Jun. 2015), PP 44-51
www.iosrjournals.org
DOI: 10.9790/0661-17364451 www.iosrjournals.org 44 | Page
A New Approach for Video Encryption Based on Modified AES
Algorithm
Asst. Prof: Dr. Salim Ali Abaas1,
Ahmed Kareem Shibeeb2
Dept. of Computer Science, College of Education, Al-MustansiryaUniversity, Baghdad, Iraq
Abstract: The securityof videoapplications such as commercial videos, military videos and othershave become
an important field of research recently. One of the most secure algorithms is Advanced Encryption Standard
(AES) algorithm;however this algorithm is inefficient for dealing with video encryption due to its slowness
property. This paper proposes a new modifiedof AES to make it more suitable for encrypting digital video. The
Modification focuses on the slowest transformations in original AES which is mix columnstransformationsand
replace them with newHenon map chaoticbased mask and one mix columns transformation. Resulting in a
significant reduction in encryption and decryption time and enhance the security level of AES algorithm, and
also the key space is increased as observed in the simulation results of proposed system.
Keywords: AES-128, Chaotic mask, Henon map, Sub-Byte, Mix columns.
I. Introduction
1.1 Background
With the rapid progress of Digital Communication Technologythe security of digital image/video plays
a significant role in computing technology. Recently, the main considerationin data storage and transmission is
theinformation security [1]. An increasing amount and security sensitivity of the information, such as audio,
images, video and other multimedia applications make it requires quick and safe ways to achieve its security [2].
There are many approaches for the information security which include steganography and cryptology. The block
ciphers have played a vital role inthe science of cryptography when the Data Encryption Standard algorithm
(DES) has been introduced. The small block size and short key problemsof the DES algorithm make it more
vulnerable to Differential Cryptanalysis (DC) and Linear Cryptanalysis (LC), in addition to security problems,
the DES algorithm is slow encryption algorithm. The Advanced Encryption Standard algorithm (AES) is new
encryption standard instead of DES algorithm according to the viewpoint of National Institute of Standards and
Technology(NIST).The advanced encryption standard algorithm provides multiple keys lengths(128 bits, 192
bits and 256 bits) on the contrary of the data encryption algorithmwhich provides short key length (56 bits), as
well as the AES Very powerful against all known attacks and faster than DES algorithm.Although the accepted
speed of AES algorithm, but it is not efficient to encrypt digital video due to the large size of the video
compared to other multimedia applications [3].So,this paper proposes an appropriate modification for original
AES-128 to make it more suitable for digital video encryption.Modification will focus on the mix columns step
to modify it with new chaos based matrix to reduce the time of encryption and decryption processes, and at the
same time provide high diffusion and confusion in the proposed algorithm.
1.2 Literature Review
Several attempts have been made in the literature towardAES algorithm enhancement andmultimedia
encryption. Hephzibah and Gnanou [4] introduce a chaos-based video encryption based on the Lorenz system,
when the plainvideo was divided into frames, then checked whether the frame was a large size, it will get
macro-blocks from theframefor encryptingit. And take advantage of the Lorenz system properties for the
purpose of frame’spixels confusion. As observed in [4], the proposed system is fast and insecure.
S.Kamali et al.[5] introducea new modified for AES algorithmto decreased the pattern appearance and
to encrypt square image onlyby adjusting the shift rows step based on the first cell value of the state array , if
its value is odd, thenthe first and third rows are remaining in an original state, whereas the second and fourth
rows are shifted one and three bytes to the left, respectively.Meantime, if its value is even, then the first and
fourth rows are unchanged, while the second and third rows are shifted three and two bytes to the right,
respectively. Likewise, the proposed method in [6], ituses the same of previous method to reduce the calculation
of the video encryption completely. This modification is a quick somewhat, but not enough for
encryptingvideo. In [7], divide the plain image into blocks then reordering of the block’s pixels is performed by
changing the positions of pixels. Finally, these blocks are passed randomly to AES algorithm. This method used
to decrease the correlation between plain image and cipher image and disregards the increase in encryption
time.However, three modifications on AES algorithm is proposed by S.Wadi and N.Zaina to make it more
suitable for encrypting HD imagesby increasing AES security and reducing its computation cost and hardware
2. A New Approach For Video Encryption Based on Modified AES Algorithm
DOI: 10.9790/0661-17364451 www.iosrjournals.org 45 | Page
requirement through, using the mix columns transformation as additionaltransformation in key schedule
operation to enhance the security level, reducing the mixcolumns step in AES-128 bits to five instead of ten to
reduce the encryption time and constructing simple and one S-boxfor encryption and decryption processes to
reduce the requirement of hardware. The first modification increases the security level and requires more time
for the encryption process.On the contrary, the second modification which provides less encryptiontime and low
security level than original AES, while the third modification reduces the security level of AES as a result of the
low nonlinearity of new S-box as obtained in [8].
II. Advanced Encryption Standard Algorithm Specification
The AESis designed to agree with principles of Substitution-Permutation Network mechanism. Thus it
involves some of operations during the encryption and decryption; these operations take 4×4 matrix called the
state which represents 16 byte of data as input. There are four basic operations used over the encryption process
to encrypt the plain text which are:Substitution byteby using the Substitution Box (S-box), Shifting Rows,
Mixing Columns and XOR'ing with Round Key.However, at the decryption process the inverse of previous
steps will be used to decrypt original data which are: InvSubBytes, InvShiftRows and InvMix-Columns in
addition to AddRoundKey transformation . The sub- keys for number of rounds (Nr) thatare used in encryption
and decryption processes will be created by using an operation of the key schedule [9].
2.1. Stages of Rounds
2.1.1 Sub-Byte / Inverse Sub-Byte
The Sub-Byte function uses a substitution table (S-box) to substitute the bytes of state array. The byte
substitution step used to increase the security level of AES algorithm because it agrees with nonlinearity
requirement [10]. However, in the decryption process theInvS-box table instead of S-boxwill be used to
implement Inverse Sub-Byte operation.
2.1.2 Shift Rows/ Inverse Shift Rows
Some references assume the shift rows operation as the second operation at the encryption round; while
it can be applied before the Sub-Byte step without any effect on the algorithm. In shift rows operation the data
matrix processes in row-by-row fashion. The first row remains unchanged, whilethe rows numbered with 2, 3
and 4 of the state matrix are rotated one, two and three bytes in cyclic way to the left-side, sequentially. In
another side, the inverse shift rows operation is obtained by remaining the first row unchanged and rotating the
rows numbered with 1, 2, and 3 cyclically rotate to the right-side, with one, two and three bytes, respectively
[11].
2.1.3 Mix Columns / Inverse Mix Columns
After applying the Shift Rows operation, the Mix Columns step is performed, in this step each column in the
state array is multiplied by a known 4x4 matrix defined as follows:
The multiplication operation is implemented on this matrix is not a normal multiplication. Rather, the
multiplication operation is carried over a Galois-Field (GF), where the multiplication operation can be obtained
as follows: Multiplication by 01 means no change, multiplication by 02 means is handled as shifting byte to the
left with one bit, and multiplication by 03treated as shifting to the left, then XOR'ing with the operand [12].
The Inverse of Mix Column operation is applied by multiplying each column of a state array by another special
matrix defined as follows:
3. A New Approach For Video Encryption Based on Modified AES Algorithm
DOI: 10.9790/0661-17364451 www.iosrjournals.org 46 | Page
2.1.4 AddRoundKey / Inverse AddRoundKey
The first AddRoundKey operation is implemented with the master key before starting the regular
rounds operations of the algorithm. The AddRoundKey transformation is the part of the algorithm which takes
each byte in the state array and XOR this byte with a corresponding byte in the round key.
2.2Key Expansion (Key Schedule)
The key expansion or the key schedule is an operation of generating a number of sub-keys from the
initial key for each round to be used in the AddRoundKey operation. Therefore, the number of needed sub-keys
is equal to the number of rounds (Nr) and hence the round keys contain 44words (where each word equal to four
bytes)will be generated for AES-128. When the words indexed from 0 to 43.The first four word (W0,
W1,W2,W3) are filled with the given cipher key, however columns in locations that are a multiple of 4 (W4 ,
W8 ,W12 … etc.) will be computed by three operations which are:The RotWordThe SubWord and addthe result
of a RotWord and SubWord operations with word Wi-4 and with a Round Constant (Rcon[i])[13].
III. Chaotic HENON Map
The noticeable properties of chaotic systems which are sensitivity to the initial condition and control
parameter values, unpredictability and their capability of generating random numbers made them used over the
last years in many cryptography[13].There are many chaotic maps with multi dimension ,one of these chaotic
maps is Henonmap that is a two dimensiondiscrete-time nonlinearmapexplained by:
Yn+1 = 1 − aYn
2
+ Zn
Zn+1 = bZn
in each of the equation, the current and next chaotic states are (Yn,Zn) and (Yn+1,Zn+1) respectively, while
thevalues of a and b are map parameters. Any of the previous parameters (a, b) or initial states (Y0 ,Z0) could be
to become a key to the aforementioned map[14,15].The Henon map exhibits chaotic behavior when a ∈
[1.16,1.41] and∈ [0.2,0.3] . The parameters values that commonly used in Henonsystem are (a= 1.4, b = 0.3)
as shown in Figure (1).
IV. The Proposed Scheme
The multiplication over Galois Field is one of the greatest importance mathematical operation
appliedduring the mix column step and one of thehigh calculation and computational overhead operation in
AES [16]. Therefore, the mix columns and its inverse are two of the slower operations in the encryption and
decryption process. This is due to the fact that, it involves matrixes multiplicationover Galois Field.This
problem is opposed to adapt the original AES to encrypt video. To overcome the problem one mix columns for
first round will be performed inaddition to new chaotic maskinstead of remained mix columns steps and their
inverse in AES-128 for encrypting video frames due to the superiority of proposed scheme in terms of speed and
the sensitivity to initial conditions and control parameters and also the increase ofkey space and key sensitivity.
This modification is as shown in the following encryption and decryption algorithms:
(1)
Figure (1):The strange attractor of Henon map with control parameters values (a= 1.4, b = 0. 3) .
4. A New Approach For Video Encryption Based on Modified AES Algorithm
DOI: 10.9790/0661-17364451 www.iosrjournals.org 47 | Page
Encryption Algorithm:
The initial value (Y0 , Z0) and two control parameters (a, b) of Henon map in addition to the cipher key that
expanded into array of 176 bytes as initial key of the algorithm.
Due to the high sensitivity of the last three numbers for each output sequence, the proposed system takes
the remainder of dividing the last three number of the map equations output (Y,Z) on the 256 to convert
them into hexadecimal values, and save it in 4×4 matrix as chaotic mask.
Sort the matrix values in ascending order.
Assign the new index of sorted matrix as permutation key and matrix values as substitution key.
Read the plain video and extract its frames. Then each frame is divided into blocks of the size 128 bits that
is placed into the state array.
Add the state array with cipher key.
Substitute each byte with Sub-Byte transformation.
Apply shift rows transformation.
Use one mix columns transformation for first round and replacethe remained mix columns transformations
(from the second round to Nr-1th
round) with new chaotic maskfor scrambling the bytes positions of the
state array by using permutation key, then the scrambled state array is XORed with chaotic mask values
(substitution key).
XOR the current state array with round key.
Reassembling the encrypted frame from the encrypted state array, then collecting the cipher frames to
create a cipher video.
Decryption Algorithm:
Set the Henon map keys and cipher key which will also expand.
Construct the Henon map based chaotic mask.
Sort the chaotic mask values.
Assign the substitution and permutation keys based on the values of generated mask and index of sorted
chaotic mask, respectively.
Read the encrypted video.
Apply add round key transformation.
Perform inverse of shift rows transformation.
Use InvS-box to apply invers Sub-Byte transformation.
Reapply add round key transformation.
Perform inverse of chaotic mask stage for the first eight rounds by XOR’ing the state array with chaotic
mask values, then descrambleit by using the permutation key, however the ninth round will be involved mix
columns transformation.
Finally, re-collecting the encrypted frames for cipher video compositing, then save it.
The block diagram of the proposed scheme for encryption and decryption processes is shown Figure (2).
5. A New Approach For Video Encryption Based on Modified AES Algorithm
DOI: 10.9790/0661-17364451 www.iosrjournals.org 48 | Page
V. Simulation Results
5.1 Security Analysis
5.1.1 Key Space Analysis
The total number of various keys thatcan be used in a proposed method is also known asthe key
space.A high secure encryption system depends onthe strength of encryption keys. Whereas the key strength is
mainly dependent on the key space. In another words, the relationship between the encryption key and the
cipher message should be as complex as possible so any change of one bit of the encryption key will produce a
total different cipher message.To achieve high resistance against many attacks such as brute-force attack, the
key space of cryptosystemmust be large as possible [17]. The proposed methodconsists ofthe exist cipher key
which is 2128
in addition to four real values that provided by the initial conditions (Y0,Z0 ) and control
parameters (a, b) of Henon map, whilst each real value is 64 bits. Hence the total key space of proposed scheme
is 2384
,whichcan make the brute force attack is impossible on this proposed algorithm .
5.1.2 Key Sensitivity Test
The key sensitivity for each cryptosystem means that the encrypted videomustbecompletely
differentfrom the original video, if there is any change between encryption and decryption keys. A
strongciphering system requires large key sensitivityas much as possibleto ensure security of the system.The
proposed scheme is high sensitive to anysmall change in one of all the keys. If the keys of the proposed system
areY0=0.50000001, Z0=0.20000001, a=1.39999,b=0.200012 and a cipher key=abcd12349876efab,the key
sensitivity test of the proposed algorithm has been applied on Rhinos(45) frame by using the same key that is
used in decryption except that the value of (Y0) is slightly changed to 0.50000002 and the plainframe is
displayed in Figure(3).
5.1.3 Resistanceto Differential Cryptanalysis
The differential cryptanalysis is one of the most powerful cryptanalysis against block cipher, the
differential cryptanalysisattempts toobserve differences of the cipherframe in the tiny change of the original
frame to find the relationship between the original frame and the cipherframe. To evaluate the cryptosystem
resistanceagainst differential attack,two measures (NPCR) and (UACI) commonly used , whereas the (NPCR)
means the change rate of the number of pixels ofthe encryptedframe when only one pixel of the originalframeis
changed and the(UACI) meansthe unified average changing intensity whichgauges the average intensity of
variations between theoriginalframe and encryptedframe [19].Their definitions are as follows:
%100
),(
,
,
NM
jiDiff
NPCR
MN
ji
%100
255
),(),(1 ,
,
21
MN
ji
jiCjiC
NM
UACI
In equation (2), the Diff (i, j) is determined by the initial cipher frameC1(i, j) andciphered frame that is changed
some grey level of the pixelsC2(i, j), if C1(i, j) = C2(i, j) then Diff (i, j) = 0, otherwise, Diff (i, j) = 1.WhileM and
N in both equations (2) and (3) are the width and height of the frame. The ideal NPCR and UACI values for 8-
bit gray scale frames are 99.609% and 33.464%,respectively.
(2)
(3)
6. A New Approach For Video Encryption Based on Modified AES Algorithm
DOI: 10.9790/0661-17364451 www.iosrjournals.org 49 | Page
Table 1 shows the test results of NPCR and UACI measures for the proposed scheme that
compared with original AES algorithm . It is discovered that the NPCR and UACIvalues of the proposed
scheme are close to their ideal values. Thus, the proposedmethodhas great capacity of resistance to the plain
text attacks anddifferential attacks.
Frames
NPCR for original
AES (in %)
UACI for original
AES(in %)
NPCR for Modified
AES (in %)
UACI for Modified
AES(in %)
Rhinos (41) 99.6367 33.5693 99.6615 33.5298
Vipmosaicking(28) 99.6054 33.3138 99.6576 33.51
Shacky-Car(86) 99.5989 33.4324 99.6223 33.4046
Viplane(4) 99.58 33.3485 99.6544 33.4134
Table (1): Measurementsof NPCR and UACI for different frames.
5.2 Statistical Analysis
5.2.1 Frame Statistic Characteristic
The pixel valuesdistribution of each frame can be reflected byImage histogram. a flat histogram of
cipher frame may mean that frameresist statistic attacks [20]. Figure (4) shows the red, green and blue
channelshistograms of the originalframe and the cipherframe. We can see that, the histogram of the
cipherframeisfairly uniformdistribution. Hence the proposed method does not present any clue to employ any
statistical attack on the encrypted frame.
5.2.2 Information Entropy Analysis
Frame information entropy is defined to measure the degree of randomness ordisorder in the systemto
give a description of the frametexture [11, 15]. Whenever thehistogram analysis only shows the cipher frame
in a qualitative way, the information entropy used to get the quantitative analysis.The formula for calculation
entropy H(x) For a frame with n gray level is:
H x = − p(xi
n
i=1
) log2 p(xi)
WhereH(x)represents of the frame and P(xi) is the emergence probability of xi . If every symbol has an
equal probability, i.ex={x0 , x1, x2 ,…x2
8
-1 } and P(xi )=1/28
(i=0,1,…255), then the entropy is H(x)=8 which
corresponds to an ideal entropy of a 256 gray-scale image.
(4)
7. A New Approach For Video Encryption Based on Modified AES Algorithm
DOI: 10.9790/0661-17364451 www.iosrjournals.org 50 | Page
The entropy analysis of encryptedframe is very closed to the ideal value as obtained in Table (2).
Therefore, the proposed scheme resist the entropy attacks.
Frames Actually Entropy Cipher Frame Entropy with original AES Cipher Frame Entropy with Modified AES
Vipmosaicking(62) 7.2803 7.9972 7.9973
Rhinos (63) 6.9627 7.9973 7.9977
Shacky-Car(57) 7.0824 7.9971 7.9969
Viplane(75) 6.6389 7.9967 7.9973
Table (2): Entropy analysis of different plain and cipher frames.
5.3 Time Analysis
Theefficiency of proposed scheme have been measured with important metric to compare
amongcryptosystems is to compute the encryption and decryption time [21] . Time analysis has been
implemented under C#.net on a 2.20 GHzIntel®Core ™ i3 CPU and 2 GB RAM -HP 650 laptop.Compared to
original AES, we can show that the running speed of theproposed method is fast,when executed in the same
conditions and environment.as obtained in Table(3).
Frames
Original AES Time(ms) Modified AES Time(ms)
Encryption Decryption Encryption Decryption
Viplane(53) 389 1033 231 305
Rhinos (3) 490 1300 286 385
Vipmosaicking(4) 489 1311 286 387
Shacky-Car(30) 492 1331 287 387
Table (3): examines quantitatively the encryption and decryption
time of the original AES and proposed scheme.
VI. Conclusion
Generallyspeed and securecryptosystems are very desirable for multimedia applications.In this
paper, an efficientmethod has been introduced for video encryption based on the combination of 2D Henon
chaotic map and AES algorithm. Whereas Henon map is used to construct new chaotic mask to replace mix
columns transformations except the first mix columns due to the slowness and security of the mix columns
transformation in original AES. Efficiency of the methodhas been confirmed through above simulation results.
According to these results the proposed scheme provides high key space, high key sensitivity and less time for
encryption and decryption processes than original AES as well as itoffers high resistance against differential
and statistical attacks.
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