Advanced Encryption Standard (AES) Algorithm has been extensively applied in the present financial applications. Sub-channel attacks are one of the main problems occurred n the AES Algorithm. Asynchronous AES Architecture is one of the leading solutions of the sub-channel attacks due to its natural properties. The AES architecture with the enhanced mix column to be proposed with reduced number of transistor counts.. Then, the Verilog A modeling is used to evaluate the performance of the proposed AES Architecture. Finally, the VLSI Implementations of the AES Processor is implemented with CMOS technology 0.25 µm. By using the net list generations, the proposed AES Architecture is analyzed regarding the VLSI design environment. The simulation results of the proposed structure are performed with the minimum number of transistor counts as well as power utilizations. Moreover, the proposed CMOS technology based AES Algorithm is integrated into the backend based chip technology.
Novel Adaptive Hold Logic Circuit for the Multiplier using Add Round Key and ...IJMTST Journal
Digital multipliers are among the most critical arithmetic functional units in many applications, such as the Fourier transform, discrete cosine transforms, and digital filtering. The through put of these applications depends on multipliers, if the multipliers are too slow, the performance of entire circuits will be reduced. The negative bias temperature instability effect occurs when a PMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of a PMOS transistor and reducing the multiplier speed. Similarly, positive bias temperature instability occurs when an NMOS transistor is under positive bias. Both effects degrade the speed of the transistor and in the long term, the system may be fail due to timing violations. Therefore, it is required to design reliable high-performance multipliers. In this paper, we implement an aging aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide the higher throughput through the variable latency and can adjust the adaptive hold logic (AHL) circuit to lessen performance degradation that is due to the aging effect. The proposed design can be applied to the column bypass multiplier.
A New Approach for Video Encryption Based on Modified AES Algorithmiosrjce
IOSR Journal of Computer Engineering (IOSR-JCE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of computer engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in computer technology. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Pipelining Architecture of AES Encryption and Key Generation with Search Base...VLSICS Design
A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has the advantage of increased throughput and offers better security. Search based S-box architecture has been proposed in this paper to reduce the constraint in the hardware resources. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm. Moreover the key schedule algorithm of the AES encryption is pipelined to get the speedup.
Arm recognition encryption by using aes algorithmeSAT Journals
Abstract To provide the security of the Military confidential data we use encryption algorithm which take over reward of superior encryption algorithm. The proposed implementation using encryption algorithm was implemented on ARM 7 to encrypt and decrypt the confidential data on data storage devices such as SD card or Pen drive. The main objective of proposed implementation is to provide protection for storage devices. The ARM and encryption algorithm protect the data accessibility, reliability and privacy successfully. Since (AES) Advanced Encryption Standard algorithm is widely used in an embedded system or fixed organization. These AES algorithms are used for proper designs in defense for security. Keywords: Plain text, Cipher text, Data security, AES, Embedded System.ARM, storage device.
This document describes a proposed design for implementing the Advanced Encryption Standard (AES) on field programmable gate arrays (FPGAs) to achieve high throughput encryption of data. The design involves two efficient pipelining structures for the AES algorithm that allow tradeoffs between speed, resource usage, and power consumption. It also proposes a new key expansion scheme that increases the complexity of cracking encryption keys. The design was evaluated on several FPGA devices and achieved throughputs up to 75.9 Gbps, demonstrating its ability to meet real-time encryption demands for very high data rates like 100 Gbps. It provides guidance on efficiently pipelining the AES logic based on analysis of the algorithm's operations and FPGA architectures.
PERFORMANCE ANALYSIS OF SYMMETRIC KEY CIPHERS IN LINEAR AND GRID BASED SENSOR...cscpconf
The linear and grid based Wireless Sensor Networks (WSN) are formed by applications where
objects being monitored are either placed in linear or grid based form. E.g. monitoring oil,
water or gas pipelines; perimeter surveillance; monitoring traffic level of city streets, goods
warehouse monitoring. The security of data is a critical issue for all such applications and as
the devices used for the monitoring purpose have several resource constraints (bandwidth,
storage capacity, battery life); it is significant to have a lightweight security solution. Therefore,
we consider symmetric key based solutions proposed in the literature as asymmetric based
solutions require more computation, energy and storage of keys. We analyse the symmetric
ciphers with respect to the performance parameters: RAM, ROM consumption and number of
CPU cycles. We perform this simulation analysis in Contiki Cooja by considering an example
scenario on two different motes namely: Sky and Z1. The aim of this analysis is to come up with
the best suited symmetric key based cipher for the linear and grid based WSN.
A new partial image encryption method for document images using variance base...IJECEIAES
The proposed method partially and completely encrypts the gray scale Document images. The complete image encryption is also performed to compare the performance with the existing encryption methods. The partial encryption is carried out by segmenting the image using the Quad-tree decomposition method based on the variance of the image block. The image blocks with uniform pixel levels are considered insignificant blocks and others the significant blocks. The pixels in the significant blocks are permuted by using 1D Skew tent chaotic map. The partially encrypted image blocks are further permuted using 2D Henon map to increase the security level and fed as input to complete encryption. The complete encryption is carried out by diffusing the partially encrypted image. Two levels of diffusion are performed. The first level simply modifies the pixels in the partially encrypted image with the Bernoulli’s chaotic map. The second level establishes the interdependency between rows and columns of the first level diffused image. The experiment is conducted for both partial and complete image encryption on the Document images. The proposed scheme yields better results for both partial and complete encryption on Speed, statistical and dynamical attacks. The results ensure better security when compared to existing encryption schemes.
LOW AREA FPGA IMPLEMENTATION OF DROMCSLA-QTL ARCHITECTURE FOR CRYPTOGRAPHIC A...IJNSA Journal
Nowadays, several techniques are implemented for the cryptosystems to provide security in communication systems. The major issues detected in conventional methods are the weakness against different attack, unacceptable data expansion, and slow performance speed. In this paper, a method Dual-port Read Only Memory-Carry Select Adder-Quantitative Trait Loci (DROM-CSLA-QTL) is introduced, which utilizes lower area than the existing method. The proposed system is implemented using DROM-CSLA, which occupies less area. The DROM-CLSA-QTL algorithm is implemented using tools such as MATLAB and Model Sim. Further for FPGA implementation, Virtex 4, Virtex 5 and Virtex 6 devices are used to determine the number of Lookup Tables (LUTs), slices, flip-flops, area and frequency. Mean, Variance and Covariance are evaluated in the MATLAB.
Novel Adaptive Hold Logic Circuit for the Multiplier using Add Round Key and ...IJMTST Journal
Digital multipliers are among the most critical arithmetic functional units in many applications, such as the Fourier transform, discrete cosine transforms, and digital filtering. The through put of these applications depends on multipliers, if the multipliers are too slow, the performance of entire circuits will be reduced. The negative bias temperature instability effect occurs when a PMOS transistor is under negative bias (Vgs = −Vdd), increasing the threshold voltage of a PMOS transistor and reducing the multiplier speed. Similarly, positive bias temperature instability occurs when an NMOS transistor is under positive bias. Both effects degrade the speed of the transistor and in the long term, the system may be fail due to timing violations. Therefore, it is required to design reliable high-performance multipliers. In this paper, we implement an aging aware multiplier design with a novel adaptive hold logic (AHL) circuit. The multiplier is able to provide the higher throughput through the variable latency and can adjust the adaptive hold logic (AHL) circuit to lessen performance degradation that is due to the aging effect. The proposed design can be applied to the column bypass multiplier.
A New Approach for Video Encryption Based on Modified AES Algorithmiosrjce
IOSR Journal of Computer Engineering (IOSR-JCE) is a double blind peer reviewed International Journal that provides rapid publication (within a month) of articles in all areas of computer engineering and its applications. The journal welcomes publications of high quality papers on theoretical developments and practical applications in computer technology. Original research papers, state-of-the-art reviews, and high quality technical notes are invited for publications.
Pipelining Architecture of AES Encryption and Key Generation with Search Base...VLSICS Design
A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has the advantage of increased throughput and offers better security. Search based S-box architecture has been proposed in this paper to reduce the constraint in the hardware resources. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm. Moreover the key schedule algorithm of the AES encryption is pipelined to get the speedup.
Arm recognition encryption by using aes algorithmeSAT Journals
Abstract To provide the security of the Military confidential data we use encryption algorithm which take over reward of superior encryption algorithm. The proposed implementation using encryption algorithm was implemented on ARM 7 to encrypt and decrypt the confidential data on data storage devices such as SD card or Pen drive. The main objective of proposed implementation is to provide protection for storage devices. The ARM and encryption algorithm protect the data accessibility, reliability and privacy successfully. Since (AES) Advanced Encryption Standard algorithm is widely used in an embedded system or fixed organization. These AES algorithms are used for proper designs in defense for security. Keywords: Plain text, Cipher text, Data security, AES, Embedded System.ARM, storage device.
This document describes a proposed design for implementing the Advanced Encryption Standard (AES) on field programmable gate arrays (FPGAs) to achieve high throughput encryption of data. The design involves two efficient pipelining structures for the AES algorithm that allow tradeoffs between speed, resource usage, and power consumption. It also proposes a new key expansion scheme that increases the complexity of cracking encryption keys. The design was evaluated on several FPGA devices and achieved throughputs up to 75.9 Gbps, demonstrating its ability to meet real-time encryption demands for very high data rates like 100 Gbps. It provides guidance on efficiently pipelining the AES logic based on analysis of the algorithm's operations and FPGA architectures.
PERFORMANCE ANALYSIS OF SYMMETRIC KEY CIPHERS IN LINEAR AND GRID BASED SENSOR...cscpconf
The linear and grid based Wireless Sensor Networks (WSN) are formed by applications where
objects being monitored are either placed in linear or grid based form. E.g. monitoring oil,
water or gas pipelines; perimeter surveillance; monitoring traffic level of city streets, goods
warehouse monitoring. The security of data is a critical issue for all such applications and as
the devices used for the monitoring purpose have several resource constraints (bandwidth,
storage capacity, battery life); it is significant to have a lightweight security solution. Therefore,
we consider symmetric key based solutions proposed in the literature as asymmetric based
solutions require more computation, energy and storage of keys. We analyse the symmetric
ciphers with respect to the performance parameters: RAM, ROM consumption and number of
CPU cycles. We perform this simulation analysis in Contiki Cooja by considering an example
scenario on two different motes namely: Sky and Z1. The aim of this analysis is to come up with
the best suited symmetric key based cipher for the linear and grid based WSN.
A new partial image encryption method for document images using variance base...IJECEIAES
The proposed method partially and completely encrypts the gray scale Document images. The complete image encryption is also performed to compare the performance with the existing encryption methods. The partial encryption is carried out by segmenting the image using the Quad-tree decomposition method based on the variance of the image block. The image blocks with uniform pixel levels are considered insignificant blocks and others the significant blocks. The pixels in the significant blocks are permuted by using 1D Skew tent chaotic map. The partially encrypted image blocks are further permuted using 2D Henon map to increase the security level and fed as input to complete encryption. The complete encryption is carried out by diffusing the partially encrypted image. Two levels of diffusion are performed. The first level simply modifies the pixels in the partially encrypted image with the Bernoulli’s chaotic map. The second level establishes the interdependency between rows and columns of the first level diffused image. The experiment is conducted for both partial and complete image encryption on the Document images. The proposed scheme yields better results for both partial and complete encryption on Speed, statistical and dynamical attacks. The results ensure better security when compared to existing encryption schemes.
LOW AREA FPGA IMPLEMENTATION OF DROMCSLA-QTL ARCHITECTURE FOR CRYPTOGRAPHIC A...IJNSA Journal
Nowadays, several techniques are implemented for the cryptosystems to provide security in communication systems. The major issues detected in conventional methods are the weakness against different attack, unacceptable data expansion, and slow performance speed. In this paper, a method Dual-port Read Only Memory-Carry Select Adder-Quantitative Trait Loci (DROM-CSLA-QTL) is introduced, which utilizes lower area than the existing method. The proposed system is implemented using DROM-CSLA, which occupies less area. The DROM-CLSA-QTL algorithm is implemented using tools such as MATLAB and Model Sim. Further for FPGA implementation, Virtex 4, Virtex 5 and Virtex 6 devices are used to determine the number of Lookup Tables (LUTs), slices, flip-flops, area and frequency. Mean, Variance and Covariance are evaluated in the MATLAB.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance evaluation of ecc in single and multi( eliptic curve)Danilo Calle
The document discusses performance evaluation of ECC (Elliptic Curve Cryptography) implementation on FPGA-based embedded systems using single and dual processor architectures. It explores implementing ECC using a single MicroBlaze soft processor core and a dual MicroBlaze core design with shared memory for inter-processor communication. Experimental results show the dual core design improves throughput by 3.3x over the single core design, encrypting data 3.3 times faster, but utilizes more resources and power due to the additional processor core.
The document contains 46 multiple choice questions related to various topics in computer science including computer hardware, programming, data structures, operating systems, databases, and networking. Each question is followed by multiple choice answers for selection.
Design of A New Lightweight Encryption for Embedded SecurityIRJET Journal
The document describes a proposed new lightweight encryption algorithm called PRESENT GRP for embedded security applications. It is designed to have low power consumption, small memory footprint, and provide security. The algorithm combines the substitution box of the existing PRESENT algorithm with a new group random permutation (GRP) layer, which provides confusion and can permute bits faster than a lookup table. Simulation results show PRESENT GRP requires less gate equivalents and memory than existing lightweight algorithms like PRESENT, making it suitable for constrained embedded devices.
Scanned document compression using block based hybrid video codecMuthu Samy
Sybian Technologies Pvt Ltd
Final Year Projects & Real Time live Projects
JAVA(All Domains)
DOTNET(All Domains)
ANDROID
EMBEDDED
VLSI
MATLAB
Project Support
Abstract, Diagrams, Review Details, Relevant Materials, Presentation,
Supporting Documents, Software E-Books,
Software Development Standards & Procedure
E-Book, Theory Classes, Lab Working Programs, Project Design & Implementation
24/7 lab session
Final Year Projects For BE,ME,B.Sc,M.Sc,B.Tech,BCA,MCA
PROJECT DOMAIN:
Cloud Computing
Networking
Network Security
PARALLEL AND DISTRIBUTED SYSTEM
Data Mining
Mobile Computing
Service Computing
Software Engineering
Image Processing
Bio Medical / Medical Imaging
Contact Details:
Sybian Technologies Pvt Ltd,
No,33/10 Meenakshi Sundaram Building,
Sivaji Street,
(Near T.nagar Bus Terminus)
T.Nagar,
Chennai-600 017
Ph:044 42070551
Mobile No:9790877889,9003254624,7708845605
Mail Id:sybianprojects@gmail.com,sunbeamvijay@yahoo.com
Moldable pipelines for CNNs on heterogeneous edge devicesLEGATO project
The LEGaTO project received funding from the European Union to develop a framework for efficiently running CNNs on heterogeneous edge devices. The framework implements a brief online training to find a near-optimal pipeline configuration that balances performance across different compute resources. It generates high-throughput CNN pipelines for edge devices containing variable core configurations on a single chip by leveraging computational hints during interface-guided partitioning and online adaptation of pipeline stages.
Layers of Computer Science, ISA and uArch Alexander Titov 20 September 2014.li50916ku
This document describes the different layers of abstraction in computer architecture from the application layer down to the physics layer. It focuses on the instruction set architecture (ISA) and microarchitecture layers. The ISA defines the machine language and hardware structures available to programmers. The microarchitecture defines the detailed implementation of hardware structures and operations not visible to programmers. The document uses MIPS as an example ISA and explains key ISA concepts like data formats, memory addressing, registers, and common instruction types.
A secure image steganography based on burrows wheeler transform and dynamic b...IJECEIAES
In modern public communication networks, digital data is massively transmitted through the internet with a high risk of data piracy. Steganography is a technique used to transmit data without arousing suspicion of secret data existence. In this paper, a color image steganography technique is proposed in spatial domain. The cover image is segmented into non-overlapping blocks which are scattered among image size window using Burrows Wheeler transform before embedding. Secret data is embedded in each block according to its sequence in the Burrows Wheeler transform output. The hiding method is an operation of an exclusive-or between a virtual bit which is generated from the most significant bit and the least significant bits of the cover pixel. Results of the algorithm are analyzed according to its degradation of the output image and embedding capacity. The results are also compared with other existing methods.
International Refereed Journal of Engineering and Science (IRJES)irjes
International Refereed Journal of Engineering and Science (IRJES) is a leading international journal for publication of new ideas, the state of the art research results and fundamental advances in all aspects of Engineering and Science. IRJES is a open access, peer reviewed international journal with a primary objective to provide the academic community and industry for the submission of half of original research and applications
Fpga implementation of encryption and decryption algorithm based on aeseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
OMT: A DYNAMIC AUTHENTICATED DATA STRUCTURE FOR SECURITY KERNELSIJCNCJournal
We introduce a family of authenticated data structures — Ordered Merkle Trees (OMT) — and illustrate
their utility in security kernels for a wide variety of sub-systems. Specifically, the utility of two types of
OMTs: a) the index ordered merkle tree (IOMT) and b) the range ordered merkle tree (ROMT), are
investigated for their suitability in security kernels for various sub-systems of Border Gateway Protocol
(BGP), the Internet’s inter-autonomous system routing infrastructure. We outline simple generic security
kernel functions to maintain OMTs, and sub-system specific security kernel functionality for BGP subsystems
(like registries, autonomous system owners, and BGP speakers/routers), that take advantage of
OMTs.
Simple regenerating codes: Network Coding for Cloud StorageKevin Tong
The document presents Simple Regenerating Codes (SRC) for efficient data repair in cloud storage systems. SRC combines MDS codes for reliability with XOR operations to allow repair using minimal bandwidth and disk I/O. Simulations show SRC reduces storage costs compared to replication and maintains high reliability while improving repair scalability through reduced repair bandwidth and disk accesses.
This document summarizes a paper that presents two parallel algorithms for batched range searching on a mesh-connected SIMD computer. The first algorithm is average-case efficient and based on cell division. The second algorithm is worst-case efficient and uses a divide-and-conquer approach. Both algorithms were implemented and experimentally evaluated on a MasPar MP-1 computer. The paper also provides background on mesh-connected SIMD computers and describes common operations like sorting that are used in the algorithms.
Biomedical image transmission based on Modified feistal algorithmijcsit
This document presents a high-performance hardware implementation of a biomedical image encryption system using a modified Feistal algorithm. The encryption algorithm is based on DES with a novel key scheduling technique. The encrypted images are unintelligible but have high clarity when decrypted. The system is implemented on an FPGA and achieves an encryption rate of 35.5 Gbit/s. It uses different keys each clock cycle, making the encrypted images very difficult to break.
The document introduces the National Supercomputer Center in Tianjin (NSCC-TJ) and its TH-1A supercomputer system. It describes that NSCC-TJ is sponsored by the Chinese government to provide high performance computing services. It then provides details about the TH-1A system including its hybrid CPU and GPU architecture, proprietary interconnect network, 262TB of memory and 2PB of storage. It also summarizes the system's software stack including the Kylin Linux operating system, compilers, programming environment and visualization system.
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Pipelining Architecture of AES Encryption and Key Generation with Search Base...VLSICS Design
A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has the advantage of increased throughput and offers better security. Search based S-box architecture has been proposed in this paper to reduce the constraint in the hardware resources. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm. Moreover the key schedule algorithm of the AES encryption is pipelined to get the speedup.
32 9139 it rtl modelling for the cipher blcok ((edit lafi)IAESIJEECS
The demand of satellite communication, the security algorithms are to be designed in the board. The information from the satellite to the ground is required the data security with the cryptographic algorithms. Advanced encryption standard (AES) is one of the promising cryptographic algorithms for the terrestrial communication. In this paper, the encryption and decryption is mainly focused on the cipher block chaining (CBC) mode for achieving the high secured data transmission. For efficient data transmission, the AES algorithm is implemented by using CBC mode. The proposed work is designed by using RTL modeling and also the minimum numbers of logical elements are used for implementation.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
This document summarizes a study that analyzed the performance of the AES-128 encryption algorithm using CBC mode on wireless sensor network motes. The study implemented AES-128 encryption and decryption with a 128-bit key on TinyOS motes. It found that AES-128 CBC provided reliable encryption for sensor networks and its performance was analyzed by measuring encryption time and energy consumption for different plaintext sizes and network scales. The encryption and decryption processes used the same 128-bit key and performed 10 rounds of AES transformations as specified for a 128-bit key.
This document describes the implementation of the AES (Advanced Encryption Standard) algorithm using a fully pipelined design on an FPGA. It first provides background on the AES algorithm, including its key components and previous hardware implementations. It then details the proposed fully pipelined design, which implements each of AES's 10 rounds as separate pipeline stages to achieve high throughput. Key generation is also pipelined internally. Simulation results show the design achieves a throughput higher than previous reported implementations.
A design of a fast parallel pipelined implementation of aes advanced encrypti...ijcsit
The Advanced Encryption Standard (AES) algorithm is a symmetric block cipher which operates on a
sequence of blocks each consists of 128, 192 or 256 bits. Moreover, the cipher key for the AES algorithm is
a sequence of 128, 192 or 256 bits. AES algorithm has many sources of parallelism. In this paper, a design
of parallel AES on the multiprocessor platform is presented. While most of the previous designs either use
pipelined parallelization or take advantage of the Mix_Column parallelization, our design is based on
combining pipelining of rounds and parallelization of Mix_Column and Add_Round_Key transformations.
This model is divided into two levels: the first is pipelining different rounds, while the second is through
parallelization of both the Add_Round_Key and the Mix_Column transformations. Previous work proposed
for pipelining AES algorithm was based on using nine stages, while, we propose the use of eleven stages in
order to exploit the sources of parallelism in both initial and final round. This enhances the system
performance compared to previous designs. Using two-levels of parallelization benefits from the highly
independency of Add_Round_Key and Mix_Column/ Inv_Mix_Colum transformations. The analysis shows
that the parallel implementation of the AES achieves a better performance. The analysis shows that using
pipeline increases significantly the degree of improvement for both encryption and decryption by
approximately 95%. Moreover, parallelizing Add_Round_Key and Mix_Column/ Inv_Mix_Column
transformations increases the degree of improvement by approximately 98%. This leads to the conclusion
that the proposed design is scalable and is suitable for real-time applications
This paper presents 16 software implementations of the Advanced Encryption Standard (AES) cipher mapped to a fine-grained many-core processor array. The implementations explore different levels of data and task parallelism. The smallest design uses 6 cores for offline key expansion and 8 cores for online expansion, while the largest uses 107 and 137 cores respectively. Compared to other software platforms, the designs achieve 3.5-15.6 times higher throughput per chip area and 8.2-18.1 times higher energy efficiency.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance evaluation of ecc in single and multi( eliptic curve)Danilo Calle
The document discusses performance evaluation of ECC (Elliptic Curve Cryptography) implementation on FPGA-based embedded systems using single and dual processor architectures. It explores implementing ECC using a single MicroBlaze soft processor core and a dual MicroBlaze core design with shared memory for inter-processor communication. Experimental results show the dual core design improves throughput by 3.3x over the single core design, encrypting data 3.3 times faster, but utilizes more resources and power due to the additional processor core.
The document contains 46 multiple choice questions related to various topics in computer science including computer hardware, programming, data structures, operating systems, databases, and networking. Each question is followed by multiple choice answers for selection.
Design of A New Lightweight Encryption for Embedded SecurityIRJET Journal
The document describes a proposed new lightweight encryption algorithm called PRESENT GRP for embedded security applications. It is designed to have low power consumption, small memory footprint, and provide security. The algorithm combines the substitution box of the existing PRESENT algorithm with a new group random permutation (GRP) layer, which provides confusion and can permute bits faster than a lookup table. Simulation results show PRESENT GRP requires less gate equivalents and memory than existing lightweight algorithms like PRESENT, making it suitable for constrained embedded devices.
Scanned document compression using block based hybrid video codecMuthu Samy
Sybian Technologies Pvt Ltd
Final Year Projects & Real Time live Projects
JAVA(All Domains)
DOTNET(All Domains)
ANDROID
EMBEDDED
VLSI
MATLAB
Project Support
Abstract, Diagrams, Review Details, Relevant Materials, Presentation,
Supporting Documents, Software E-Books,
Software Development Standards & Procedure
E-Book, Theory Classes, Lab Working Programs, Project Design & Implementation
24/7 lab session
Final Year Projects For BE,ME,B.Sc,M.Sc,B.Tech,BCA,MCA
PROJECT DOMAIN:
Cloud Computing
Networking
Network Security
PARALLEL AND DISTRIBUTED SYSTEM
Data Mining
Mobile Computing
Service Computing
Software Engineering
Image Processing
Bio Medical / Medical Imaging
Contact Details:
Sybian Technologies Pvt Ltd,
No,33/10 Meenakshi Sundaram Building,
Sivaji Street,
(Near T.nagar Bus Terminus)
T.Nagar,
Chennai-600 017
Ph:044 42070551
Mobile No:9790877889,9003254624,7708845605
Mail Id:sybianprojects@gmail.com,sunbeamvijay@yahoo.com
Moldable pipelines for CNNs on heterogeneous edge devicesLEGATO project
The LEGaTO project received funding from the European Union to develop a framework for efficiently running CNNs on heterogeneous edge devices. The framework implements a brief online training to find a near-optimal pipeline configuration that balances performance across different compute resources. It generates high-throughput CNN pipelines for edge devices containing variable core configurations on a single chip by leveraging computational hints during interface-guided partitioning and online adaptation of pipeline stages.
Layers of Computer Science, ISA and uArch Alexander Titov 20 September 2014.li50916ku
This document describes the different layers of abstraction in computer architecture from the application layer down to the physics layer. It focuses on the instruction set architecture (ISA) and microarchitecture layers. The ISA defines the machine language and hardware structures available to programmers. The microarchitecture defines the detailed implementation of hardware structures and operations not visible to programmers. The document uses MIPS as an example ISA and explains key ISA concepts like data formats, memory addressing, registers, and common instruction types.
A secure image steganography based on burrows wheeler transform and dynamic b...IJECEIAES
In modern public communication networks, digital data is massively transmitted through the internet with a high risk of data piracy. Steganography is a technique used to transmit data without arousing suspicion of secret data existence. In this paper, a color image steganography technique is proposed in spatial domain. The cover image is segmented into non-overlapping blocks which are scattered among image size window using Burrows Wheeler transform before embedding. Secret data is embedded in each block according to its sequence in the Burrows Wheeler transform output. The hiding method is an operation of an exclusive-or between a virtual bit which is generated from the most significant bit and the least significant bits of the cover pixel. Results of the algorithm are analyzed according to its degradation of the output image and embedding capacity. The results are also compared with other existing methods.
International Refereed Journal of Engineering and Science (IRJES)irjes
International Refereed Journal of Engineering and Science (IRJES) is a leading international journal for publication of new ideas, the state of the art research results and fundamental advances in all aspects of Engineering and Science. IRJES is a open access, peer reviewed international journal with a primary objective to provide the academic community and industry for the submission of half of original research and applications
Fpga implementation of encryption and decryption algorithm based on aeseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
OMT: A DYNAMIC AUTHENTICATED DATA STRUCTURE FOR SECURITY KERNELSIJCNCJournal
We introduce a family of authenticated data structures — Ordered Merkle Trees (OMT) — and illustrate
their utility in security kernels for a wide variety of sub-systems. Specifically, the utility of two types of
OMTs: a) the index ordered merkle tree (IOMT) and b) the range ordered merkle tree (ROMT), are
investigated for their suitability in security kernels for various sub-systems of Border Gateway Protocol
(BGP), the Internet’s inter-autonomous system routing infrastructure. We outline simple generic security
kernel functions to maintain OMTs, and sub-system specific security kernel functionality for BGP subsystems
(like registries, autonomous system owners, and BGP speakers/routers), that take advantage of
OMTs.
Simple regenerating codes: Network Coding for Cloud StorageKevin Tong
The document presents Simple Regenerating Codes (SRC) for efficient data repair in cloud storage systems. SRC combines MDS codes for reliability with XOR operations to allow repair using minimal bandwidth and disk I/O. Simulations show SRC reduces storage costs compared to replication and maintains high reliability while improving repair scalability through reduced repair bandwidth and disk accesses.
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International Journal of Engineering Research and DevelopmentIJERD Editor
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VLSI Architecture for Nano Wire Based Advanced Encryption Standard (AES) with the Efficient Multiplicative Inverse Unit
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.8, No.6, December 2017
DOI : 10.5121/vlsic.2017.8602 15
VLSI ARCHITECTURE FOR NANO WIRE BASED
ADVANCED ENCRYPTION STANDARD (AES)
WITH THE EFFICIENT MULTIPLICATIVE
INVERSE UNIT
K.Sandyarani1
and P. Nirmal Kumar2
1
Research Scholar, Department of ECE, Sathyabama University, Chennai, India
2
Associate Professor, Department of ECE, College of Engineering, Guindy, Anna
University, Chennai, India
ABSTRACT
Advanced Encryption Standard (AES) Algorithm has been extensively applied in the present financial
applications. Sub-channel attacks are one of the main problems occurred n the AES Algorithm.
Asynchronous AES Architecture is one of the leading solutions of the sub-channel attacks due to its natural
properties. The AES architecture with the enhanced mix column to be proposed with reduced number of
transistor counts.. Then, the Verilog A modeling is used to evaluate the performance of the proposed AES
Architecture. Finally, the VLSI Implementations of the AES Processor is implemented with CMOS
technology 0.25 µm. By using the net list generations, the proposed AES Architecture is analyzed regarding
the VLSI design environment. The simulation results of the proposed structure are performed with the
minimum number of transistor counts as well as power utilizations. Moreover, the proposed CMOS
technology based AES Algorithm is integrated into the backend based chip technology.
KEYWORDS
Advanced Encryption Standard, Sub-Channel, Mix-Column, Verilog A, Complementary metal oxide
semiconductor, Nano-technology.
1. INTRODUCTION
Data security is one of the major concerns for the data communication systems. There is various
security algorithms are developed for protecting the information in the data communication
networks. Advanced Encryption Standard (AES) is one of the highly secured algorithms for data
protections. The AES Algorithm is used to encrypt and decrypt the data by the three sizes of bits
that are, 128,192 and 256The symmetric algorithm in AES and Asymmetric algorithm in RSA are
the two classes of encryption methods which are commonly used. The first algorithm uses the
same key for encrypting or decrypting data and is very fast due to its small key size but suffers
the exchange of this key. Whereas the next one is secure because it uses a pair of keys, one for
encrypting and another for decrypting, but suffers the encryption slowness due to complex
computations involved by large key size (1024 bits and more).The FIPS-197 specification, some
standard modes of operation. The Easiest and simplest is the electronic code book (ECB).
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.8, No.6, December 2017
16
However, this may occur some security vulnerabilities. Additional resistance to attack may be
achieved using one o f the recognized feedback modes, for instance, cipher block chaining
(CBC).
However, the benefit of a feedback mode can limit the effectiveness of pipelining in a hardware
implementation. Feedback modes have concentrated on the patterns which only need the encipher
data path such as output feedback (OFB) mode. In recent years, the asynchronous circuit has been
giving the more requirements due to the security problems and power utilizations. The state of the
system and hand shake clock signals are observed by using the external and internal events of the
asynchronous circuits. These circuits are also described as the self-timed circuits due to the circuit
timing assumptions.
2. RELATED WORKS
Linearity and Non-Linearity technique based AES algorithms are required the Look-Up-Tables
(LUT) to register the substitution value of the given input data. [1] Described the reduction of the
complexity in the multiplicative inverse unit for the Advanced Encryption Standard (AES)
algorithm. Multiplicative Inverse is one of the essential parts of the AES Structure. (Galois Field)
GF 24
based multiplicative inverse unit is used to overcome the disadvantage of the conventional
Linearity and Non-Linearity based AES algorithm. Composite S-Box based multiplicative inverse
unit offers the minimum number of logical elements counts as the well efficient computational
delay. Composite S-Box and a Multiplicative Inverse unit are used to provide the efficient
cryptographic techniques.
The proposed sub-bytes transformation eliminates the usage of the LUT. The proposed composite
field is used as the data path for the Sub-bytes and Inv-Sub-Bytes transformations. [2] Presented
the efficient Mix-column transformation for high-speed AES Architecture. The decompose the
inversion is mainly proposed in this work to provide the efficient structure with the minimized
area and smaller critical path. Non-LUT based algorithm can provide the further efficiency in
pipelining architecture. Mix-column transformations are designed by using simple logical ex-or
gates to reduce the logical elements counts as well as efficient power utilizations.
Counter mode based architecture is used to overcome the limitation compare than the ECB and
CBC modes. [3] Analyze the counter mode based AES algorithm with the nonlinearity based S-
box architecture. The Counter mode based AES has not encrypted the data directly like ECB and
CBC modes. The counter mode is first encrypting the counter, and then the values are XOR’ed.
At each successive block of the system, the counter value is incremented by one. The virtual s-
box is generated at the each input data. In the virtual S-Box, the input data are mapped by the
virtual s-box to provide the encrypted data. The proposed virtual s-box architecture is performed
with the efficient power utilizations as well as fewer area utilizations.
By using the CBC mode, the plaintext of the encrypted data is XOR’ed with the last cipher text of
the architecture. [4] Stated the eliminate the single event upsets (SEU) and composite s-box into
the AES modes of operations. Each cipher text is performed depend on the plain text in the CBC
mode. The counter mode is used to overcome the disadvantage of the CBC mode. The counter
mode is generating the arbitrary value for encryption and then performs the XOR operations. The
reductions of the ADP (Area-Delay Product) are highly achieved by the LUT fewer Field
transformations.
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.8, No.6, December 2017
17
The proposed composite field arithmetic based S-Box transformations are providing better logical
elements utilizations. [5] Described Complementary Metal-Oxide Semiconductor (CMOS)
technology based Advanced Encryption and Decryption. The proposed composite S-Box design
is implemented by using the 250 nm CMOS technology. By implementing the backend design,
the power utilizations are highly achieved. Composite s-box unit is entirely designed by using the
simple ex-or gates. In inverse ISO technique, the logical gates are highly reduced compare than
the conventional ISO technique.
3. MEMORY ARCHITECTURE BASED AES COMPUTING
In general, the data stored in the memory cell is divided from the general processors and also that
data is connected to I/O’s. All the input data are required to mitigate, and the information is
rewrite. Due to the rewrite functions, the I/O congestion occurs and also the overall system
performance is affected due to the data mitigations. The power utilization of the system is also
highly increased by the storage of the large data. There are some more I/O's are included in the
data at high frequency is used to conquer the congestion problem in theoretical. This theoretical
solution is limited by the CMOS scalability. The data preprocessing is required only the perform
with a small amount of the intermediate results and also the data traffic is highly reduced by the
data pre processing. The Memory logic architecture has performed some pre processing stages at
locally.
Figure 1: Flow Diagram for Advanced Encryption Standard Architecture
The memory logic in the single cell causes the overhead of the higher data and also the
communication traffic is limited. Due to the memory array, there is possibility of unique data is
available at a given time sequence. Single data working process is also leading the wastage of the
additional resources and high power utilizations. One more disadvantage of the memory logic is,
the storage has required the ordering of the information.
4. PROPOSED NANO WIRE BASED AES ARCHITECTURE
In memory based architecture, the data encryption is performed openly on the cells. The
encryption data has required the model for simulating the algorithms. The domain wall can
perform the one input data at a given time. To separate the nano wires, the domain wall can
perform the multiple data at a time that is the concurrent operations are achieved. Each row of the
binary data is required to store in the domain wall Nano wire is develop the shift function of the
algorithm. For performing the storage purpose, there are four Nano wires are required. The
reduction of the circular left shift operations current is achieved by the redundant bits.
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.8, No.6, December 2017
18
A) Sub-Bytes:
The S-Box design is implemented by using the general LUT that is; there are some memory based
logical elements are needed for the S-Box design. The conventional S-Box design is performed
with the highest number of the logical elements counts as well as the computational delay. To
reduce the logical elements counts, the S-Box architecture is implemented by using the Nano wire
based structure. By using the domain wall Nano wires, the power is reduced. The memory
elements and decoders are collective for reducing the logical elements counts as well as the
power utilizations.
Figure 2: Proposed S-Box Architecture based Nano-Wire
B) Shift Rows:
The shift rows are performed by using the general shift property in the conventional method. In
the proposed computations, the input data are shifted by using the unique domain wall Nano wire
based property. The input data are operated circularly by performing the left shift operations of
the binary data in the Nano wires. In the shift rows transformations, the second row of the matrix
is to be left shifted by cylindrically. The second rows of the matrix are shifted by the two bits, and
the third row of the matrix is shifted by the three bits. The virtual cycle on the Nano wire is
formed to eliminate the storage of MSB to LSB. The circular left shifted rows are used to
determine the Nano wire bits added in the system. In the Nano wire system, the various numbers
of input bits are performed concurrently, so the congestion occurrence is highly avoided by using
the Nano wire technology
C) Add-Round Key:
The Add round key stage is to be performing the bitwise XOR operations with the corresponding
bytes of the matrix. In general, the standard XOR gate is used for the add round key operations.
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.8, No.6, December 2017
19
Figure 3: Nano wire based XOR Gate and Symbolic View of the XOR Gate
This Add-Round fundamental structure is performed with the highest number of area utilizations
as well as the power utilization is not efficient. Nano-Wire based X-OR gate is used to implement
the add-round key stage. In the proposed Nano wire based XOR gate, the output data are
measured by using the low or high resistance value of the Multiple Tunnel Junction (MTJ).
D) Mix-Column Transformations:
The proposed mix column transformations are implemented by using the Domain-Wall Nano
wire based EX-OR gate and Domain wall Nano wire LUT. In traditional mix column
transformations, the memory based architecture is used for the both mix and inverse mix column
matrix. In the proposed mix column design, the X-time multiplications and domain wall based
XOR gate. There are two x-time multiplications are required for the mix-column process. The X-
time 2 is slightly different from the general integer multiplications by left shift, and the bit is
XORed. The proposed mix column transformations utilize the domain wall based XOR gate and
domain wall based LUT, and also the xtime multiplications are used to generate the efficiency.
Figure 4: Proposed Mix-Column Transformations
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.8, No.6, December 2017
20
5. EXPERIMENTAL RESULTS
The validations of the proposed AES Encryption and Decryption by using CMOS technology is
implemented by using Tanner EDA and their synthesis results are carried out by using the T-
Spice. Verilog A Language is used to implement the proposed design in the spice simulator to
evaluate the performance characteristics. Nano-Wire based XOR Gate, and the Multiplicative
inverse unit is shown in Fig.5 and Fig.6.
Figure 5: Schematic Design of the proposed Multiplicative Inverse Unit
Figure 6: Proposed Nano-Wire based XOR gate
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.8, No.6, December 2017
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Figure 7: Synthesis Results for Number of MOSFET Counts
6. CONCLUSION
In this paper, the domain wall Nano-wire based Advanced Encryption Standard (AES)
Encryption and Decryption have been implemented with the Verilog A Language. By using
Verilog A Language, the proposed Nano-Wire based Multiplicative Inverse Unit is designed by
using the CMOS Technology with the help of Tanner EDA and Spice simulator. The proposed
schematic design is implemented in the S-Edit, and the synthesis results are carried out by using
the Spice simulations. In the traditional method, the AES Encryption and Decryption is
performed based on the Domino logic. The Domino logic is generating the high number of logical
elements counts due to the general blocks of the CMOS technology. To reduce the number of
logical elements counts, the AES Architecture is implemented by using the Domain wall Nano-
Wire Technology. By using the Domain wall Nano-wire technology, the transistor sizing is
highly reduced compare than the traditional logic.
REFERENCES
[1] Sandyarani, K. and Kumar, P.N., “Low Power and low CMOS Complexity Based Composite S-Box
for Aes Encryption and Aes Decryption”, Indian Journal of Applied Research, Vol. 5, No. 10, 2016.
[2] Sandyarani, K. and Kumar, P.N., 2014, Design of High-Speed AES – 128 using Novel MixColumn
Transformation & Sub Bytes. Journal of computer applications (JCA), 2014.
[3] Sandyarani, K. and Kumar, P.N., 2013, July. Design and analysis of AES-CM with nonlinearity S-
box architecture. In Current Trends in Engineering and Technology (ICCTET), 2013 International
Conference on (pp. 252-254). IEEE.
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.8, No.6, December 2017
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