This document presents a high-performance hardware implementation of a biomedical image encryption system using a modified Feistal algorithm. The encryption algorithm is based on DES with a novel key scheduling technique. The encrypted images are unintelligible but have high clarity when decrypted. The system is implemented on an FPGA and achieves an encryption rate of 35.5 Gbit/s. It uses different keys each clock cycle, making the encrypted images very difficult to break.
Hardware Implementation of Algorithm for Cryptanalysisijcisjournal
Cryptanalysis of block ciphers involves massive computations which are independent of each other and can
be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low
cost Field Programmable Gate Arrays (FPGA’s), building special purpose hardware for computationally
intensive applications has now become possible. For this the Data Encryption Standard (DES) is used as a
proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on
FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are compared
and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this
work is to make cryptanalysis faster and better.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
This document summarizes a research paper that proposes a new block cipher cryptographic symmetric key algorithm called the "TACIT Encryption Technique." The algorithm uses a unique mathematical logic approach along with a new key distribution system. It is implemented in a hardware chip using VHDL programming language on a Network-on-Chip model for secure data transmission. Experimental results show encryption and decryption of 128-bit blocks using an 8-bit key through simulation in Modelsim. The algorithm aims to provide better security, speed and flexibility than existing algorithms like DES, AES and RSA.
LOW AREA FPGA IMPLEMENTATION OF DROMCSLA-QTL ARCHITECTURE FOR CRYPTOGRAPHIC A...IJNSA Journal
Nowadays, several techniques are implemented for the cryptosystems to provide security in communication systems. The major issues detected in conventional methods are the weakness against different attack, unacceptable data expansion, and slow performance speed. In this paper, a method Dual-port Read Only Memory-Carry Select Adder-Quantitative Trait Loci (DROM-CSLA-QTL) is introduced, which utilizes lower area than the existing method. The proposed system is implemented using DROM-CSLA, which occupies less area. The DROM-CLSA-QTL algorithm is implemented using tools such as MATLAB and Model Sim. Further for FPGA implementation, Virtex 4, Virtex 5 and Virtex 6 devices are used to determine the number of Lookup Tables (LUTs), slices, flip-flops, area and frequency. Mean, Variance and Covariance are evaluated in the MATLAB.
With increasing technology development in field of communication and Electronic devices, there is a need for better security service for information transfer in Medical Sectors, Banking, Financial and in other IoT applications etc. Fight against security attacks is of prime importance. Through Cryptographic techniques we can provide Authenticity as well as Confidentiality for the user data. In this paper, hardware implementation has been described for a real-time application of speech data encryption and decryption using AES algorithm along with the speech recognition using cross correlation technique. Verilog programming environment is used for AES cryptography whereas MATLAB is used for Speech recognition. ASIC design on AES core is implemented using Cadence tools. Number of gates, area and power used by AES core design has been drastically reduced by specifying wide range of constraints during front end designing. In Backend designing, layout of AES design, which is the physical geometric representation is also developed.
This document summarizes a research paper that proposes a microcontroller-based cryptosystem using the Tiny Encryption Algorithm (TEA) combined with a Key Generation Unit (KGU). The KGU uses timers in the microcontroller to generate random bits for encryption keys. The cryptosystem can operate in serial or wireless transmission modes. Performance analysis shows the cryptosystem has improved throughput and decreased execution time compared to TEA alone. Randomness testing of the generated keys indicates distinct random bits. In conclusion, the system provides moderate security and simplicity for applications requiring secured data transfer with low cost and memory constraints.
Secure Image Transmission for Cloud Storage System Using Hybrid SchemeIJERD Editor
- Data over the cloud is transferred or transmitted between servers and users. Privacy of that
data is very important as it belongs to personal information. If data get hacked by the hacker, can be
used to defame a person’s social data. Sometimes delay are held during data transmission. i.e. Mobile
communication, bandwidth is low. Hence compression algorithms are proposed for fast and efficient
transmission, encryption is used for security purposes and blurring is used by providing additional
layers of security. These algorithms are hybridized for having a robust and efficient security and
transmission over cloud storage system.
An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithmijsrd.com
A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S -box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.
Hardware Implementation of Algorithm for Cryptanalysisijcisjournal
Cryptanalysis of block ciphers involves massive computations which are independent of each other and can
be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low
cost Field Programmable Gate Arrays (FPGA’s), building special purpose hardware for computationally
intensive applications has now become possible. For this the Data Encryption Standard (DES) is used as a
proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on
FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are compared
and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this
work is to make cryptanalysis faster and better.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
This document summarizes a research paper that proposes a new block cipher cryptographic symmetric key algorithm called the "TACIT Encryption Technique." The algorithm uses a unique mathematical logic approach along with a new key distribution system. It is implemented in a hardware chip using VHDL programming language on a Network-on-Chip model for secure data transmission. Experimental results show encryption and decryption of 128-bit blocks using an 8-bit key through simulation in Modelsim. The algorithm aims to provide better security, speed and flexibility than existing algorithms like DES, AES and RSA.
LOW AREA FPGA IMPLEMENTATION OF DROMCSLA-QTL ARCHITECTURE FOR CRYPTOGRAPHIC A...IJNSA Journal
Nowadays, several techniques are implemented for the cryptosystems to provide security in communication systems. The major issues detected in conventional methods are the weakness against different attack, unacceptable data expansion, and slow performance speed. In this paper, a method Dual-port Read Only Memory-Carry Select Adder-Quantitative Trait Loci (DROM-CSLA-QTL) is introduced, which utilizes lower area than the existing method. The proposed system is implemented using DROM-CSLA, which occupies less area. The DROM-CLSA-QTL algorithm is implemented using tools such as MATLAB and Model Sim. Further for FPGA implementation, Virtex 4, Virtex 5 and Virtex 6 devices are used to determine the number of Lookup Tables (LUTs), slices, flip-flops, area and frequency. Mean, Variance and Covariance are evaluated in the MATLAB.
With increasing technology development in field of communication and Electronic devices, there is a need for better security service for information transfer in Medical Sectors, Banking, Financial and in other IoT applications etc. Fight against security attacks is of prime importance. Through Cryptographic techniques we can provide Authenticity as well as Confidentiality for the user data. In this paper, hardware implementation has been described for a real-time application of speech data encryption and decryption using AES algorithm along with the speech recognition using cross correlation technique. Verilog programming environment is used for AES cryptography whereas MATLAB is used for Speech recognition. ASIC design on AES core is implemented using Cadence tools. Number of gates, area and power used by AES core design has been drastically reduced by specifying wide range of constraints during front end designing. In Backend designing, layout of AES design, which is the physical geometric representation is also developed.
This document summarizes a research paper that proposes a microcontroller-based cryptosystem using the Tiny Encryption Algorithm (TEA) combined with a Key Generation Unit (KGU). The KGU uses timers in the microcontroller to generate random bits for encryption keys. The cryptosystem can operate in serial or wireless transmission modes. Performance analysis shows the cryptosystem has improved throughput and decreased execution time compared to TEA alone. Randomness testing of the generated keys indicates distinct random bits. In conclusion, the system provides moderate security and simplicity for applications requiring secured data transfer with low cost and memory constraints.
Secure Image Transmission for Cloud Storage System Using Hybrid SchemeIJERD Editor
- Data over the cloud is transferred or transmitted between servers and users. Privacy of that
data is very important as it belongs to personal information. If data get hacked by the hacker, can be
used to defame a person’s social data. Sometimes delay are held during data transmission. i.e. Mobile
communication, bandwidth is low. Hence compression algorithms are proposed for fast and efficient
transmission, encryption is used for security purposes and blurring is used by providing additional
layers of security. These algorithms are hybridized for having a robust and efficient security and
transmission over cloud storage system.
An Efficient FPGA Implementation of the Advanced Encryption Standard Algorithmijsrd.com
A proposed FPGA-based implementation of the Advanced Encryption Standard (AES) algorithm is presented in this paper. This implementation is compared with other works to show the efficiency. The design uses an iterative looping approach with block and key size of 128 bits, lookup table implementation of S -box. This gives low complexity architecture and easily achieves low latency as well as high throughput. Simulation results, performance results are presented and compared with previous reported designs.
The document summarizes a block-based image transformation and encryption algorithm. It divides images into blocks that are rearranged to decrease correlation between pixels. The transformed image is then encrypted with Blowfish. Three cases using different block sizes were tested. Results showed that using smaller blocks decreased correlation and increased entropy, strengthening encryption. The technique enhances security by transforming before encrypting with Blowfish.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
International Refereed Journal of Engineering and Science (IRJES)irjes
International Refereed Journal of Engineering and Science (IRJES) is a leading international journal for publication of new ideas, the state of the art research results and fundamental advances in all aspects of Engineering and Science. IRJES is a open access, peer reviewed international journal with a primary objective to provide the academic community and industry for the submission of half of original research and applications
This document summarizes a research paper that proposes a new approach for complex encryption and decryption of data. The approach uses a combination of public key infrastructure and RC6 algorithm. It divides plaintext into blocks, uses one block as an encryption key, and inserts the key into the ciphertext based on a private position. Performance analysis shows the proposed approach encrypts and decrypts data faster than the AES algorithm. Security analysis indicates the approach is secure against known attacks based on correlation analysis and information entropy tests. The approach provides improved security and performance for encrypting network data.
An Image Encryption using Chaotic Based Cryptosystemxlyle
NAME: MUHAMAD LUQMAN NULHAKIM BIN MANSOR
NO MATRIC: BTBL16043975
COURSE: ISM (SK) KESELAMATAN RANGKAIAN KOMPUTER
SUPERVISOR: PROF. MADYA DR AFENDEE BIN MOHAMED
UNIVERSITI SULTAN ZAINAL ABIDIN
11.secure compressed image transmission using self organizing feature mapsAlexander Decker
This document summarizes a research paper that proposes a method for secure compressed image transmission using self-organizing feature maps. The method involves compressing images using SOFM-based vector quantization, entropy coding the results, and encrypting the compressed data using a scrambler before transmission. Simulation results show the method achieves a compression ratio of up to 38:1 while providing security, outperforming JPEG compression by up to 1 dB. The paper presents the technical details and evaluation of the proposed secure image transmission system.
Extended of TEA: A 256 bits block cipher algorithm for image encryption IJECEIAES
This paper introduces an effective image encryption approach that merges a chaotic map and polynomial with a block cipher. According to this scheme, there are three levels of encryption. In the first level, pixel positions of the image are scuffled into blocks randomly based on a chaotic map. In the second level, the polynomials are constructed by taking N unused pixels from the permuted blocks as polynomial coefficients. Finally, the third level a proposed secret-key block cipher called extended of tiny encryption algorithm (ETEA) is used. The proposed ETEA algorithm increased the block size from 64-bit to 256-bit by using F-function in type three Feistel network design. The key schedule generation is very straightforward through admixture the entire major subjects in the identical manner for every round. The proposed ETEA algorithm is word-oriented, where wholly internal operations are executed on words of 32 bits. So, it is possible to efficiently implement the proposed algorithm on smart cards. The results of the experimental demonstration that the proposed encryption algorithm for all methods are efficient and have high security features through statistical analysis using histograms, correlation, entropy, randomness tests, and the avalanche effect.
MICRO ROTOR ENHANCED BLOCK CIPHER DESIGNED FOR EIGHT BITS MICRO-CONTROLLERS (...IJNSA Journal
The sensor network is a wireless network environment that consists of the many sensors of lightweight and
low-power. Authentication between nodes is very vital for network reliability and the integrity of
information collected by these nodes. Therefore, encryption algorithm for the implementation of reliable
sensor network environments is required to the applicable sensor network. This paper gives a new
proposed cryptosystem (MREBC) that is designed for 8 bits microcontroller systems. MREBC uses the
concept of rotor enhanced block cipher which was initially proposed by the author in [NRSC 2002] on the
first version of REBC. MREBC uses rotors to achieve two basic cryptographic operations; permutation,
and substitution. Round key is generated using rotor too, which is used to achieve ciphertext key
dependency. Rotors implemented using 8 bits successive affine transformation, which achieves memoryless,
normalized ciphertext statistics, and small processing speed trend. The strength of this system is
compared with the RIJNDAEL (AES) cipher. MREBC cipher gives excellent results from security
characteristics and statistical point of view of. communication efficiency of MREBC is compared with AES
through measuring performance by plaintext size, and cost of operation per hop according to the network
scale. Arduino microcontroller board is used to implement both MREBC, and AES in order to compare the
performance of algorithms. Authors suggests to use MREBC to implement a reliable sensor network
environments.
A Novel Structure with Dynamic Operation Mode for Symmetric-Key Block CiphersIJNSA Journal
Modern Internet protocols support several modes of operation in encryption tasks for data confidentiality
to keep up with varied environments and provide the various choices, such as multi-mode IPSec support.
To begin with we will provide a brief background on the modes of operation for symmetric-key block
ciphers. Different block cipher modes of operation have distinct characteristics. For example, the cipher
block chaining (CBC) mode is suitable for operating environments that require self-synchronizing
capabilities, and the output feedback (OFB) mode requires encryption modules only. When using
symmetric-key block cipher algorithms such as the Advanced Encryption Standard (AES), users
performing information encryption often encounter difficulties selecting a suitable mode of operation.
This paper describes a structure for analyzing the block operation mode combination. This unified
operation structure (UOS) combines existing common and popular block modes of operation. UOS does
multi-mode of operation with most existing popular symmetric-key block ciphers and do not only consist
of encryption mode such as electronic codebook (ECB) mode, cipher block chaining (CBC) mode, cipher
feedback (CFB) mode and output feedback (OFB) mode, that provides confidentiality but also message
authentication mode such as the cipher block chaining message authentication code (CBC-MAC) in
cryptography. In Cloud Computing, information exchange frequently via the Internet and on-demand.
This research provides an overview and information useful for approaching low-resource hardware
implementation, which is proper to ubiquitous computing devices such as a sensor mote or an RFID tag.
The use of the method is discussed and an example is given. This provides a common solution for multimode and this is very suitable for ubiquitous computing with several resources and environments. This
study indicates a more effectively organized structure for symmetric-key block ciphers to improve their
application scenarios. We can get that it is flexible in modern communication applications.
Hardware implementation of the serpent block cipher using fpga technologyIAEME Publication
This document describes a hardware implementation of the Serpent block cipher using FPGA technology. It provides an overview of the Serpent encryption and decryption algorithms, which operate on 128-bit blocks using a 128, 192, or 256-bit key. The algorithms involve an initial/final permutation, 32 rounds of key mixing, S-box substitutions, and linear transformations. The document also discusses specifics of implementing Serpent on a Xilinx Spartan-6 FPGA, including using the FPGA's look-up tables. Comparisons to other symmetric block ciphers are provided.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Hybrid compression based stationary wavelet transformsOmar Ghazi
This document presents a hybrid compression approach for images that uses Stationary Wavelet Transforms (SWT), Back Propagation Neural Network (BPNN), and Lempel-Ziv-Welch (LZW) compression. The approach involves: 1) preprocessing the image, 2) applying SWT, 3) converting to a 1D vector using zigzag scan, and 4) hybrid compression using BPNN vector quantization and LZW lossless compression. Experimental results show the SWT with BPNN and LZW achieves the highest compression ratios but the longest processing time, while SWT with Run Length encoding has a lower ratio but shorter time. The hybrid approach combines lossy and lossless compression techniques to obtain a
Video Encryption and Decryption with Authentication using Artificial Neural N...IOSR Journals
Abstract :Multimedia data security is becoming important with the continuous increase of digital communications on internet. With the rapid development of various multimedia technologies, more and more multimedia data are generated and transmitted in the medical, commercial, and military fields, which may include some sensitive information which should not be accessed by or can only be partially exposed to the general users. . The encryption algorithms developed to secure text data are not suitable for multimedia application because of the large data size and real time constraint. Therefore, there is a great demand for secured data storage and transmission techniques. Information security has traditionally been ensured with data encryption and authentication techniques. The secrecy of communication is maintained by secret key exchange. In effect the strength of the algorithm depends solely on the length of the key. The presented work aims at secure video transmission using randomness in encryption algorithm, thereby creating more confusion to obtain the original data. The security of the original cipher has been enhanced by addition of impurities to misguide the cryptanalyst. Since the encryption process is one way function, the artificial neural networks are best suited for this purpose as they possess features like high security, no distortion and its ability to perform for non linear input-output characteristics, In the presented work the need for key exchange is also eliminated, which is otherwise a perquisite for most of the algorithms used today. The proposed work finds its application in medical imaging systems, military image database communication and confidential video conferencing, and similar such application. The results are obtained through the use of MATLAB 7.14.0 Keywords: Artificial Neural networks, Back propagation algorithm, video encryption and decryption, cipher and decipher.
COMPARATIVE ANALYSIS OF DIFFERENT ENCRYPTION TECHNIQUES IN MOBILE AD HOC NETW...IJCNCJournal
In this paper a detailed analysis of Data Encryption Standard (DES), Triple DES (3DES) and Advanced
Encryption Standard (AES) symmetric encryption algorithms in MANET was done using the Network
Simulator 2 (NS-2) in terms of energy consumption, data transfer time, End-to-End delay time and
throughput with varying data sizes. Two simulation models were adopted: the first simulates the network
performance assuming the availability of the common key, and the second simulates the network
performance including the use of the Diffie-Hellman Key Exchange (DHKE) protocol in the key
management phase. The obtained simulation results showed the superiority of AES over DES by 65%, 70%
and 83% in term of the energy consumption, data transfer time, and network throughput respectively. On
the other hand, the results showed that AES is better than 3DES by approximately 90% for all of the
performance metrics. Based on these results the AES was the recommended encryption scheme.
SELECTIVE ENCRYPTION OF IMAGE BY NUMBER MAZE TECHNIQUEijcisjournal
Due to enormous increase in the usage of computers and mobiles, today’s world is currently flooded with huge volumes of data. This paper is primarily focused on multimedia data and how it can be protected from unwanted attacks. Sharing of multimedia data is easy and very efficient, it has been a customary practice to share multimedia data but there is no proper encryption technique to encrypt multimedia data. Sharing of multimedia data over unprotected networks using DCT algorithm and then applying selective encryption-based algorithm has never been adequately studied. This paper introduces a new selective encryption-based security system which will transfer data with protection even in unauthenticated network. Selective encryption-based security system will also minimize time during encryption process which there by achieves efficiency. The data in the image is transmitted over a network is discriminated using DCT transform and then it will be selectively encrypted using Number Puzzle technique, and thus provides security from unauthorized access. This paper discusses about numeric puzzle-based encryption technique
and how it can achieve security and integrity for multimedia data over traditional encryption technique.
The document discusses various topics related to image encryption, including encryption algorithms, evolutionary algorithms, chaos theory, and swarm intelligence. It provides an analysis and comparison of existing image encryption algorithms such as techniques using digital signatures, SCAN-based compression and encryption, and mirror-like scrambling according to a chaotic binary sequence. It also describes encryption methods using double random phase encoding of color images and decomposing images into vectors before applying traditional cryptosystems.
Innovex aims to merge all improvement projects into the business excellence framework to achieve integration, improve project quality, motivate employee participation in continuous improvement, and create an innovation culture. An award night called Innovex recognizes the best teams for their projects based on return on investment, with over 6000 projects filtered down to 22 winners who are celebrated with their spouses.
Vidapp - Android Application for learner driversRichwell Phinias
The Android Vidapp is an application created by Kevin Ngalonde for Android devices to help users study and prepare for provisional driver's license exams. It contains questions and answers from exam sections on signs and car diagrams for revision, and indicates whether the user's answer is correct or wrong. The application's structure includes an exam section for theory questions with their correct answers. It is one of Ngalonde's Android projects, who is available to answer any questions about the app.
Writers can market themselves through various methods including leaflets, print media, websites, blogging, and social networking sites. A survey found that 50% of people felt social networking sites were the best way for a new business to advertise as they provide worldwide reach and easy accessibility. While traditional print advertising is declining due to increased online options, print still targets specific audiences. Websites are also effective but require promotion so people know how to find the site. The most successful promotions utilize multiple methods rather than relying on just one.
This document describes a biomodeling software called BioMeteorology that allows users to construct and modify models using various components, run completed models to generate outputs like graphs, tables and maps, and provides a sample model of the lifecycle stages of the white stem borer insect pest. The software contains modules, functions and processes to build models and simulate their outputs.
The document summarizes a block-based image transformation and encryption algorithm. It divides images into blocks that are rearranged to decrease correlation between pixels. The transformed image is then encrypted with Blowfish. Three cases using different block sizes were tested. Results showed that using smaller blocks decreased correlation and increased entropy, strengthening encryption. The technique enhances security by transforming before encrypting with Blowfish.
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
International Refereed Journal of Engineering and Science (IRJES)irjes
International Refereed Journal of Engineering and Science (IRJES) is a leading international journal for publication of new ideas, the state of the art research results and fundamental advances in all aspects of Engineering and Science. IRJES is a open access, peer reviewed international journal with a primary objective to provide the academic community and industry for the submission of half of original research and applications
This document summarizes a research paper that proposes a new approach for complex encryption and decryption of data. The approach uses a combination of public key infrastructure and RC6 algorithm. It divides plaintext into blocks, uses one block as an encryption key, and inserts the key into the ciphertext based on a private position. Performance analysis shows the proposed approach encrypts and decrypts data faster than the AES algorithm. Security analysis indicates the approach is secure against known attacks based on correlation analysis and information entropy tests. The approach provides improved security and performance for encrypting network data.
An Image Encryption using Chaotic Based Cryptosystemxlyle
NAME: MUHAMAD LUQMAN NULHAKIM BIN MANSOR
NO MATRIC: BTBL16043975
COURSE: ISM (SK) KESELAMATAN RANGKAIAN KOMPUTER
SUPERVISOR: PROF. MADYA DR AFENDEE BIN MOHAMED
UNIVERSITI SULTAN ZAINAL ABIDIN
11.secure compressed image transmission using self organizing feature mapsAlexander Decker
This document summarizes a research paper that proposes a method for secure compressed image transmission using self-organizing feature maps. The method involves compressing images using SOFM-based vector quantization, entropy coding the results, and encrypting the compressed data using a scrambler before transmission. Simulation results show the method achieves a compression ratio of up to 38:1 while providing security, outperforming JPEG compression by up to 1 dB. The paper presents the technical details and evaluation of the proposed secure image transmission system.
Extended of TEA: A 256 bits block cipher algorithm for image encryption IJECEIAES
This paper introduces an effective image encryption approach that merges a chaotic map and polynomial with a block cipher. According to this scheme, there are three levels of encryption. In the first level, pixel positions of the image are scuffled into blocks randomly based on a chaotic map. In the second level, the polynomials are constructed by taking N unused pixels from the permuted blocks as polynomial coefficients. Finally, the third level a proposed secret-key block cipher called extended of tiny encryption algorithm (ETEA) is used. The proposed ETEA algorithm increased the block size from 64-bit to 256-bit by using F-function in type three Feistel network design. The key schedule generation is very straightforward through admixture the entire major subjects in the identical manner for every round. The proposed ETEA algorithm is word-oriented, where wholly internal operations are executed on words of 32 bits. So, it is possible to efficiently implement the proposed algorithm on smart cards. The results of the experimental demonstration that the proposed encryption algorithm for all methods are efficient and have high security features through statistical analysis using histograms, correlation, entropy, randomness tests, and the avalanche effect.
MICRO ROTOR ENHANCED BLOCK CIPHER DESIGNED FOR EIGHT BITS MICRO-CONTROLLERS (...IJNSA Journal
The sensor network is a wireless network environment that consists of the many sensors of lightweight and
low-power. Authentication between nodes is very vital for network reliability and the integrity of
information collected by these nodes. Therefore, encryption algorithm for the implementation of reliable
sensor network environments is required to the applicable sensor network. This paper gives a new
proposed cryptosystem (MREBC) that is designed for 8 bits microcontroller systems. MREBC uses the
concept of rotor enhanced block cipher which was initially proposed by the author in [NRSC 2002] on the
first version of REBC. MREBC uses rotors to achieve two basic cryptographic operations; permutation,
and substitution. Round key is generated using rotor too, which is used to achieve ciphertext key
dependency. Rotors implemented using 8 bits successive affine transformation, which achieves memoryless,
normalized ciphertext statistics, and small processing speed trend. The strength of this system is
compared with the RIJNDAEL (AES) cipher. MREBC cipher gives excellent results from security
characteristics and statistical point of view of. communication efficiency of MREBC is compared with AES
through measuring performance by plaintext size, and cost of operation per hop according to the network
scale. Arduino microcontroller board is used to implement both MREBC, and AES in order to compare the
performance of algorithms. Authors suggests to use MREBC to implement a reliable sensor network
environments.
A Novel Structure with Dynamic Operation Mode for Symmetric-Key Block CiphersIJNSA Journal
Modern Internet protocols support several modes of operation in encryption tasks for data confidentiality
to keep up with varied environments and provide the various choices, such as multi-mode IPSec support.
To begin with we will provide a brief background on the modes of operation for symmetric-key block
ciphers. Different block cipher modes of operation have distinct characteristics. For example, the cipher
block chaining (CBC) mode is suitable for operating environments that require self-synchronizing
capabilities, and the output feedback (OFB) mode requires encryption modules only. When using
symmetric-key block cipher algorithms such as the Advanced Encryption Standard (AES), users
performing information encryption often encounter difficulties selecting a suitable mode of operation.
This paper describes a structure for analyzing the block operation mode combination. This unified
operation structure (UOS) combines existing common and popular block modes of operation. UOS does
multi-mode of operation with most existing popular symmetric-key block ciphers and do not only consist
of encryption mode such as electronic codebook (ECB) mode, cipher block chaining (CBC) mode, cipher
feedback (CFB) mode and output feedback (OFB) mode, that provides confidentiality but also message
authentication mode such as the cipher block chaining message authentication code (CBC-MAC) in
cryptography. In Cloud Computing, information exchange frequently via the Internet and on-demand.
This research provides an overview and information useful for approaching low-resource hardware
implementation, which is proper to ubiquitous computing devices such as a sensor mote or an RFID tag.
The use of the method is discussed and an example is given. This provides a common solution for multimode and this is very suitable for ubiquitous computing with several resources and environments. This
study indicates a more effectively organized structure for symmetric-key block ciphers to improve their
application scenarios. We can get that it is flexible in modern communication applications.
Hardware implementation of the serpent block cipher using fpga technologyIAEME Publication
This document describes a hardware implementation of the Serpent block cipher using FPGA technology. It provides an overview of the Serpent encryption and decryption algorithms, which operate on 128-bit blocks using a 128, 192, or 256-bit key. The algorithms involve an initial/final permutation, 32 rounds of key mixing, S-box substitutions, and linear transformations. The document also discusses specifics of implementing Serpent on a Xilinx Spartan-6 FPGA, including using the FPGA's look-up tables. Comparisons to other symmetric block ciphers are provided.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
Hybrid compression based stationary wavelet transformsOmar Ghazi
This document presents a hybrid compression approach for images that uses Stationary Wavelet Transforms (SWT), Back Propagation Neural Network (BPNN), and Lempel-Ziv-Welch (LZW) compression. The approach involves: 1) preprocessing the image, 2) applying SWT, 3) converting to a 1D vector using zigzag scan, and 4) hybrid compression using BPNN vector quantization and LZW lossless compression. Experimental results show the SWT with BPNN and LZW achieves the highest compression ratios but the longest processing time, while SWT with Run Length encoding has a lower ratio but shorter time. The hybrid approach combines lossy and lossless compression techniques to obtain a
Video Encryption and Decryption with Authentication using Artificial Neural N...IOSR Journals
Abstract :Multimedia data security is becoming important with the continuous increase of digital communications on internet. With the rapid development of various multimedia technologies, more and more multimedia data are generated and transmitted in the medical, commercial, and military fields, which may include some sensitive information which should not be accessed by or can only be partially exposed to the general users. . The encryption algorithms developed to secure text data are not suitable for multimedia application because of the large data size and real time constraint. Therefore, there is a great demand for secured data storage and transmission techniques. Information security has traditionally been ensured with data encryption and authentication techniques. The secrecy of communication is maintained by secret key exchange. In effect the strength of the algorithm depends solely on the length of the key. The presented work aims at secure video transmission using randomness in encryption algorithm, thereby creating more confusion to obtain the original data. The security of the original cipher has been enhanced by addition of impurities to misguide the cryptanalyst. Since the encryption process is one way function, the artificial neural networks are best suited for this purpose as they possess features like high security, no distortion and its ability to perform for non linear input-output characteristics, In the presented work the need for key exchange is also eliminated, which is otherwise a perquisite for most of the algorithms used today. The proposed work finds its application in medical imaging systems, military image database communication and confidential video conferencing, and similar such application. The results are obtained through the use of MATLAB 7.14.0 Keywords: Artificial Neural networks, Back propagation algorithm, video encryption and decryption, cipher and decipher.
COMPARATIVE ANALYSIS OF DIFFERENT ENCRYPTION TECHNIQUES IN MOBILE AD HOC NETW...IJCNCJournal
In this paper a detailed analysis of Data Encryption Standard (DES), Triple DES (3DES) and Advanced
Encryption Standard (AES) symmetric encryption algorithms in MANET was done using the Network
Simulator 2 (NS-2) in terms of energy consumption, data transfer time, End-to-End delay time and
throughput with varying data sizes. Two simulation models were adopted: the first simulates the network
performance assuming the availability of the common key, and the second simulates the network
performance including the use of the Diffie-Hellman Key Exchange (DHKE) protocol in the key
management phase. The obtained simulation results showed the superiority of AES over DES by 65%, 70%
and 83% in term of the energy consumption, data transfer time, and network throughput respectively. On
the other hand, the results showed that AES is better than 3DES by approximately 90% for all of the
performance metrics. Based on these results the AES was the recommended encryption scheme.
SELECTIVE ENCRYPTION OF IMAGE BY NUMBER MAZE TECHNIQUEijcisjournal
Due to enormous increase in the usage of computers and mobiles, today’s world is currently flooded with huge volumes of data. This paper is primarily focused on multimedia data and how it can be protected from unwanted attacks. Sharing of multimedia data is easy and very efficient, it has been a customary practice to share multimedia data but there is no proper encryption technique to encrypt multimedia data. Sharing of multimedia data over unprotected networks using DCT algorithm and then applying selective encryption-based algorithm has never been adequately studied. This paper introduces a new selective encryption-based security system which will transfer data with protection even in unauthenticated network. Selective encryption-based security system will also minimize time during encryption process which there by achieves efficiency. The data in the image is transmitted over a network is discriminated using DCT transform and then it will be selectively encrypted using Number Puzzle technique, and thus provides security from unauthorized access. This paper discusses about numeric puzzle-based encryption technique
and how it can achieve security and integrity for multimedia data over traditional encryption technique.
The document discusses various topics related to image encryption, including encryption algorithms, evolutionary algorithms, chaos theory, and swarm intelligence. It provides an analysis and comparison of existing image encryption algorithms such as techniques using digital signatures, SCAN-based compression and encryption, and mirror-like scrambling according to a chaotic binary sequence. It also describes encryption methods using double random phase encoding of color images and decomposing images into vectors before applying traditional cryptosystems.
Innovex aims to merge all improvement projects into the business excellence framework to achieve integration, improve project quality, motivate employee participation in continuous improvement, and create an innovation culture. An award night called Innovex recognizes the best teams for their projects based on return on investment, with over 6000 projects filtered down to 22 winners who are celebrated with their spouses.
Vidapp - Android Application for learner driversRichwell Phinias
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Writers can market themselves through various methods including leaflets, print media, websites, blogging, and social networking sites. A survey found that 50% of people felt social networking sites were the best way for a new business to advertise as they provide worldwide reach and easy accessibility. While traditional print advertising is declining due to increased online options, print still targets specific audiences. Websites are also effective but require promotion so people know how to find the site. The most successful promotions utilize multiple methods rather than relying on just one.
This document describes a biomodeling software called BioMeteorology that allows users to construct and modify models using various components, run completed models to generate outputs like graphs, tables and maps, and provides a sample model of the lifecycle stages of the white stem borer insect pest. The software contains modules, functions and processes to build models and simulate their outputs.
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HARDWARE IMPLEMENTATION OF ALGORITHM FOR CRYPTANALYSISijcisjournal
Cryptanalysis of block ciphers involves massive computations which are independent of each other and can be instantiated simultaneously so that the solution space is explored at a faster rate. With the advent of low cost Field Programmable Gate Arrays (FPGA’s), building special purpose hardware for computationally intensive applications has now become possible. For this the Data Encryption Standard (DES) is used as a proof of concept. This paper presents the design for Hardware implementation of DES cryptanalysis on FPGA using exhaustive key search. Two architectures viz. Rolled and Unrolled DES architecture are compared and based on experimental result the Rolled architecture is implemented on FPGA. The aim of this work is to make cryptanalysis faster and better.
The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data also called Rijndael. The algorithm described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data. Hardware-based cryptography is used for authentication of users and of software updates and installations. Software implementations can generally not be used for this, as the cryptographic keys are stored in the PC memory during execution, and are vulnerable to malicious codes. Hardware-based encryption products can also vary in the level of protection they provide against brute force rewind attacks, Offline parallel attacks, or other cryptanalysis attacks. The algorithm was implemented in FPGA due to its flexibility and reconfiguration capability. A reconfigurable device is very convenient for a cryptography algorithm since it allows cheap and quick alterations. The implementation of pipelined cryptography hardware was used to improve performance in order to achieve higher throughput and greater parallelism. The AES hardware was implemented in three modules contains of the encryption, the decryption and the key expansion module.
A NOVEL STRUCTURE WITH DYNAMIC OPERATION MODE FOR SYMMETRIC-KEY BLOCK CIPHERSIJNSA Journal
This document proposes a unified operation structure (UOS) that combines existing block cipher modes of operation to allow for multi-mode functionality. The UOS uses three buffers to store feedback information from the previous encryption block, overcoming the typical need for separate buffers for each mode. This provides a common solution for supporting multiple modes of operation with low memory requirements, making it suitable for ubiquitous computing devices. The UOS can integrate encryption modes like ECB, CBC, CFB and OFB as well as authentication modes like CBC-MAC to provide both confidentiality and integrity.
An area and power efficient on chip communication architectures for image enc...eSAT Publishing House
1. The document describes two area and power efficient on-chip communication architectures proposed for image encryption and decryption using a single soft processor (MicroBlaze) on an FPGA.
2. The architectures are implemented using Xilinx Platform Studio on a Spartan6 FPGA. One is based on a Processor Local Bus and the other on an AMBA AXI interconnect.
3. The designs consume low power (0.67W) and occupy only 19% of FPGA resources. Experimental results show encryption and decryption of images takes 45 seconds.
IJCER (www.ijceronline.com) International Journal of computational Engineerin...ijceronline
This document describes an area optimized and pipelined FPGA implementation of the AES encryption and decryption algorithm. The AES algorithm is divided into four 32-bit units that are processed sequentially with a clock. This reduces the chip size compared to previous implementations that processed the full 128-bit blocks. Pipelining is used to increase throughput. The implementation is tested on a Spartan 3 FPGA using VHDL. It aims to achieve both high throughput and reduced hardware usage compared to prior designs.
Comparison of AES and DES Algorithms Implemented on Virtex-6 FPGA and Microbl...IJECEIAES
Encryption algorithms play a dominant role in preventing unauthorized access to important data. This paper focus on the implementations of Data Encryption Standard (DES) and Advanced Encryption Standard (AES) algorithms on Microblaze soft core Processor and also their implementations on XC6VLX240t FPGA using Verilog Hardware Description language. This paper also gives a comparison of the issues related to the hardware and software implementations of the two cryptographic algorithms.
hardware implementation of aes encryption and decryption for low area & low p...Kumar Goud
Abstract-An AES algorithm is implemented on FPGA platform to improve the safety of data in transmission. AES algorithms can be implemented on FPGA in order to speed data processing and reduce time for key generating. We achieve higher performance by maintaining standard speed and reliability with low area and power. The 128 bit AES algorithm is implements on a FPGA using VHDL language with help of Xilinx tool.
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Cryptography technique is used to provide data security. In existing cryptography technique the key generation takes place randomly. Key generation require shared key. If shared key is access by unauthorized user then security becomes disoriented. Hence existing problems are alleviated to give more security to data. In proposed system a algorithm called as Elliptic Curve Cryptography is used. The ECC generates the key by using the point on the curve. The ECC is used for generating the key by using point on the curve and encryption and decryption operation takes place through curve. In the proposed system the encryption and key generation process takes place rapidly.
This document describes the implementation of the AES (Advanced Encryption Standard) algorithm using a fully pipelined design on an FPGA. It first provides background on the AES algorithm, including its key components and previous hardware implementations. It then details the proposed fully pipelined design, which implements each of AES's 10 rounds as separate pipeline stages to achieve high throughput. Key generation is also pipelined internally. Simulation results show the design achieves a throughput higher than previous reported implementations.
New Technique Using Multiple Symmetric keys for Multilevel EncryptionIJERA Editor
In a world of accelerating communications, cryptography has become an essential component of the modern
means of communication systems. The emergence of the webas a reliable medium for commerce and
communication has made cryptography an essential component. Many algorithms or ciphers are in use
nowadays. The quality of the cipher is judged byits ability to prevent an unrelated party fromknowingthe
original content of the encrypted message. The proposed “Multilevel Encryption Model” is a cryptosystem that
adopts the basic principles of cryptography. It uses five symmetric keys (multiple)
in floating point numbers, plaintext, substitution techniques and key combinations with unintelligible
sequence to produce the ciphertext. The decryption process is also designed to reproduce the plaintext
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Implementation of Cryptography Architecture with High Secure CoreIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
LOW AREA FPGA IMPLEMENTATION OF DROMCSLA-QTL ARCHITECTURE FOR CRYPTOGRAPHIC A...IJNSA Journal
Nowadays, several techniques are implemented for the cryptosystems to provide security in communication
systems. The major issues detected in conventional methods are the weakness against different attack,
unacceptable data expansion, and slow performance speed. In this paper, a method Dual-port Read Only
Memory-Carry Select Adder-Quantitative Trait Loci (DROM-CSLA-QTL) is introduced, which utilizes
lower area than the existing method. The proposed system is implemented using DROM-CSLA, which
occupies less area. The DROM-CLSA-QTL algorithm is implemented using tools such as MATLAB and
Model Sim. Further for FPGA implementation, Virtex 4, Virtex 5 and Virtex 6 devices are used to
determine the number of Lookup Tables (LUTs), slices, flip-flops, area and frequency. Mean, Variance and
Covariance are evaluated in the MATLAB.
THE UNIFIED OPERATION STRUCTURE FOR SYMMETRIC-KEY ALGORITHMcscpconf
In Cloud Computing, information exchange frequently via the Internet and on-demand. Modern
Internet protocols support several modes of operation to keep up with varied environments and
provide the variant choice, such as SSL and IPSec support multi-mode. The different mode has
the different characters. For example: CFB/OFB can be design operating without padding with
bit size keystream output, CBC/CFB can self synchronize to avoid channel noise, and CFB/OFB
needs encryption module only. The main emphasis is placed on the problem of case by case
operation mode usage. We describe a structure for the analysis of the block operation mode
combination. This unified operation structure, called UOS, combines existing in common and
popular block modes of operation. UOS does multi-mode of operation with most existing
popular symmetric block ciphers and do not only consist of encryption mode such as ECB, CBC,
CFB and OFB, that provides confidentiality but also message authentication mode such as
CBC-MAC in cryptography. It provides low-resource hardware implementation, which is
proper to ubiquitous computing devices such as a sensor mote or an RFID tag. Our contribution
provides a common solution for multi-mode and this is very suitable for ubiquitous computing with several resources and environments. The study indicates a better well-organized structure for symmetric block ciphers so as to improve their application scenarios.
The document describes the design of a custom cryptographic processor for implementing symmetric key operations. The processor is implemented on an FPGA using Verilog. It includes instruction units to perform logical operations, arithmetic operations, and finite field arithmetic needed for symmetric key algorithms like AES, Blowfish, RC5, RC6, IDEA. The processor is pipelined for high speed and includes modules for an ALU, control unit, registers, and multiplexers. Experimental results showed the processor operates at high speed with low area and delay compared to a general purpose processor.
IMPLEMENTATION OF AES AS A CUSTOM HARDWARE USING NIOS II PROCESSORacijjournal
This document describes the implementation of the Advanced Encryption Standard (AES) algorithm as a custom hardware accelerator connected to a Nios II processor system. AES was written in VHDL and connected to the Nios II system through GPIO pins. This allows AES operations to be controlled through C code in the Nios II IDE while running the AES algorithm in hardware, improving encryption speeds significantly compared to an all-software implementation. Synthesis results showed the hardware AES implementation reduced the number of clock cycles needed for encryption by over 99% compared to running AES solely in software on the Nios II processor.
ACTIVITY SPOTTER DURING MEDICAL TREATMENT USING VISUAL CRYPTOGRAPHY TECHNIQUEIRJET Journal
This document summarizes a research paper that proposes a method for securely transmitting medical data using visual cryptography and encryption techniques. The method encrypts sensitive patient data using AES encryption with a 256-bit key before hiding the encrypted data in images using least significant bit (LSB) substitution steganography. At the receiving end, the encrypted data is extracted from the image and decrypted using AES to obtain the original medical information. The document provides details of the AES encryption and LSB hiding algorithms used, and explains how the proposed dual layer security approach combining encryption and steganography helps achieve a high level of security for transmitting sensitive medical data. Experimental results demonstrated that the encrypted data was well hidden in cover images and the method was effective for secure
Performance evaluation of ecc in single and multi( eliptic curve)Danilo Calle
The document discusses performance evaluation of ECC (Elliptic Curve Cryptography) implementation on FPGA-based embedded systems using single and dual processor architectures. It explores implementing ECC using a single MicroBlaze soft processor core and a dual MicroBlaze core design with shared memory for inter-processor communication. Experimental results show the dual core design improves throughput by 3.3x over the single core design, encrypting data 3.3 times faster, but utilizes more resources and power due to the additional processor core.
A vlsi implementation of a resource efficient and secure architecture of a b...eSAT Journals
This document discusses the VLSI implementation of a resource efficient and secure architecture for a block cipher. It proposes two designs - a throughput enhanced design and an area reduced design. The designs implement a 128-bit block cipher using the Hummingbird algorithm. Simulation results on ModelSim and synthesis results on Xilinx show that the area reduced design uses fewer logic resources than the throughput enhanced design, making it more suitable for FPGA implementation where area is a concern.
A vlsi implementation of a resource efficient and secure architecture of a b...eSAT Journals
Abstract
In today‘s modern life, the protection of data is of major concern in any kind of domian. So the understanding of cryptography architecture plays a crucial role. Advance encryption system , differential encryption system design of cryptography have few drawbacks in implementation level of low level designs. In an area concerned and power concerned parameters the above mentioned algorithms have failed in implementing. The humming bird algorithm uses block cipher which is being used in this paper for encryption and decryption using 128 bit secure key. Block cipher concentrates on converting the given original data into cipher text to make the given data more secure over the user. Two different designs of block Cipher algorithms (Throughput enhanced , Area reduced) are developed and their performance is compared in terms of area occupation using Xilinx ISE design tool with verilog language. The block cipher designs are implemented using 64 bit secure key and 128 bit secure key. The area reduced design is of the concern to have this module on the FPGA implementation in the VLSI sector.
Keywords : Cryptography, VLSI, FPGA , Block Cipher.
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Biomedical image transmission based on Modified feistal algorithm
1. International Journal of Computer Science & Information Technology (IJCSIT) Vol 5, No 3, June 2013
DOI : 10.5121/ijcsit.2013.5314 175
BIOMEDICAL IMAGE TRANSMISSION BASED ON
MODIFIED FEISTAL ALGORITHM
Jinu Elizabeth John1
1
Asst.Professor,Department of ECE, Saintgits College of Engineering,India
amritianjinu@gmail.com
ABSTRACT
This paper presents a reconfigurable, high performance hardware implementation of highly secure
biomedical image transmission system which can be used for sending medical reports in military and high
security environments. The algorithm for encryption is based on DES algorithm with a novel skew core key
scheduling. The encrypted image is not intelligible to an intruder, but the recovered image has high level of
clarity. This type of encryption can be used in applications where we need to discourage eavesdropping
from co-channel users or RF scanners. The biomedical image encryption technique is implemented on
Virtex 5 XC5VLX110T Field Programming Gate Arrays (FPGA) technology and NET FPGA. Final 16-
stage pipelined design is achieved with encryption rate of 35.5 Gbit/s and 2140 number of Configurable
logic blocks (CLBs).
KEYWORDS
Image Encryption,Security,Cryptography ,Feistal Algorithm
1. INTRODUCTION
In this era of rapid developments in internet and multimedia systems the need for effective
,secure and reliable processing ,storage and transmission of images has increased. If a highly
confidential medical image report or secret image is to be transmitted among the communicators,
then they must use a highly secure method so that the transmitted image is not interpreted by an
intruder who is attacking the communication network. So image steganography techniques are the
most inevitable module in secure image transmission as they serve as a powerful measure against
eavesdropping and are needed to ensure privacy in multimedia transmission in internet.
Encryption algorithms have been developed as a mechanism for providing this security and there
is a need to perform these algorithms on data in real time.In typical image encryptors the image is
digitized and the resulting sequence is encrypted into an unintelligible image to avoid
eavesdropping. The use of different keys in every clock cycle, make the scrambled image seem
unintelligible and very tough to break making time slot based image steganography suitable for
the most sensitive strategic communications .The use of entirely different key sets every clock
cycle improves the overall security of the device.This supports the Electronic Code Book (ECB)
mode of operation. FPGA implementation of image encryptor or decryptor was accomplished on
a Virtex 5-xc5vlx110t-3ff1100 and NET FPGA using Xilinx Foundation Series 12.1 as synthesis.
Image encryption implementations on reconfigurable hardware provides major benefits over
VLSI (very large scale integrated circuits) and software platforms since they offer high speed
similar to VLSI and high flexibility similar to software. Since the time and costs of VLSI design
and fabrication can be reduced the reconfigurable devices are attractive.
2. International Journal of Computer Science & Information Technology (IJCSIT) Vol 5, No 3, June 2013
176
In a typical image encryptions, the clear image is digitized and the digital sequence is scrambled
into an unintelligible image in order to avoid eavesdropping. The recorded image is subdivided
into smaller blocks of 64 bit. A 64 bit novel DES encryption algorithm is used to rearrange blocks
within each segment .For transmission the rearranged blocks are brought together. The use of
different keys in every clock cycle, make the scrambled image seem unintelligible and very tough
to break making time slot based image scrambling suitable for the most sensitive strategic
communications. The scrambling is based on a 16 –stage pipelined DES algorithm with a novel
skew core key scheduling. It allows simultaneous processing of 16 data blocks, resulting in an
impressing gain in speed. This the overall security of the speech scrambling improved since it
uses different keys every clock cycle and therefore the users are not restricted to the use of same
key at any time of data transfer. This design is implemented on Virtex 5 FPGA and NET FPGA
2. IMAGE SECURITY SYSTEMS
In image scrambling systems, the recorded multimedia image is modified by a known scrambling
algorithm so as to make the scrambled image unintelligible does not convey any information of
the original secret image. This image scrambling algorithm is governed by a specific code or
"key”. Different scrambled signals can be obtained if different keys are used. The image that is
thus scrambled is transmitted. At the receiver the scrambled signal is again modified by a
descrambling algorithm under the control of a specific key. This ultimately results in an image,
which resembles the original secret image exactly. In a correctly operating system, the
Scrambling Key and Descrambling Key are identical, and the descrambling algorithm is the
inverse of the scrambling algorithm. Therefore, whatever the scrambling algorithm does, the
descrambling algorithm undoes. If the Scrambling Key and Descrambling Key are different, then
the descrambling algorithm will not recover the original signal properly. This paper uses a
pipelined DES algorithm with a novel key scheduling to scramble communications.
3. BACKGROUND
In this project the scrambling and descrambling is done by means of DES algorithm. The data
encryption standard (DES) is the best known and most widely used private key encryption
algorithm developed by IBM in 1977 as a modification of an earlier system known as
Lucifer[1].The overall scheme of DES algorithm is illustrated (see Figure.1).DES is a Feistel
cipher which operates on two inputs: the 64 bit plain text to be encrypted and 56-bit secret key.
Precisely, the input key is specified as 64 bits, 8 bits of which is used for parity checking. With a
key length of 56 bits 2^56 combinations are possible, and therefore the cryptanalytic works seem
very tough. The encryption proceeds in 16 stages or rounds. Sixteen 48-bit sub keys Ki are
generated, one for each round[1],within each round, 8 fixed, carefully selected 6-to-4 bit
substitution boxes (S-boxes) are used. Thus a 64-bit plaintext is divided into 32-bit halves L0 and
R0. Each round is functionally equivalent, taking 32-bit inputs Li−1 and Ri−1 from the previous
round and producing 32-bit outputs Li and Ri for 1 ≤ i ≤16
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Fig 1 DES Algorithm Description
3.1. F function
The f function of DES algorithm is made up of four functions: Expansion, Xor, Substitution,
Permutation.A Key-dependent substitution on each of 8 characters is carried out by right half of
each round, to produce 32 output bits.(see figure 2).
3.2. Key Scheduling
In DES algorithm 16 different sub keys each of 48 bit wide is developed from a single 56 bit key.
These operations make use of tables PC1 and PC2 which are permuted choice 1 and permuted
choice 2 [6].The 8 bits of 64 bits is discarded by PC1 .The remaining 56 bits are permuted and
assigned to two 28-bit variables C and D; and then a cyclic shift operation is carried out on each
half. Both C and D are rotated either 1 or 2 bits for 16 iterations, and 48 bit keys (Ki) are selected
from the concatenated result. This process is repeated for each stage of 16 stage pipeline. In
rounds, 1, 2, 9 and 16 of Feistal algorithm the halves are shifted one position to left and for all
other rounds it is shifted to left by two places.(see figure 3).
Fig 2 f box
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Fig 3 Key Scheduling
3.3. Pipelined Implementation
The ECB mode of DES algorithm is implemented in this paper as it can be easily pipelined
[8].This pipelined DES design increases the speed and throughput of DES significantly[6]. A
combinational digital circuit can be converted into a pipelined design by dividing it into stages
and inserting buffers (registers) at proper places [2]. Adding pipeline into a combinational design
can only increase a system’s throughput. Such an approach does not reduce the delay in an
individual task.The delay will be worse than that of the non-pipelined design because of the
overhead introduced by the registers and non-ideal stage division [2].(see figure 3).
3.4 .Skew Core Implementation of DES
For the 16-stage pipelined DES design, the sub keys are pre-computed and it is necessary to
control the time at which the sub keys are available to each function f block [6]. This is
accomplished by addition of an array of D flip flops that delays the individual sub-keys by
required amount [6, 9].
Fig 4: Skew Core Key Scheduling
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4. IMAGE PROCESSING USING SKEW CORE DESIGN
Image encryptions described in this paper actually digitizes the conversation at internet and
applies a cryptographic technique to the resulting bit stream. The biomedical image to be
transmitted is divided into a number of segments each of 64 bit wide. The transformed image is
then fed to the modified DES encryption algorithm. The core concept is that a biomedical image
can be viewed as an arrangement of segments. The operation of dividing and replacing an
arrangement of the original image is referred to as transformation process. The image is thus
encrypted in blocks to produce a series of cipher texts. The cipher texts in decimal format is
combined in a matrix form to obtain the required encrypted image in Matlab. The decryption can
also be done in the reverse manner to obtain the original image. The scrambling technique
presented in this paper offers high speed and throughput alongside improved levels of security.
The encrypted and decrypted image is shown in Figure 8. To improve the initial keys and the
iterating operations, the chaotic sequence is implemented in the DES algorithm (so that the
biomedical image encryption is combined with DES algorithm )[12].
5. IMPLEMENTATION RESULTS
FPGA implementation of DES algorithm was accomplished on Virtex 5 FPGA,Xilinx as
synthesis tool and Modelsim 6.2c as simulation tool. The design was coded using Verilog HDL
language.It occupied 2140 (45%) CLB slices, 1808 (19%) slice Flip Flops and 187 (80%) I/Os.
Intially a latency of 16 clock cycles is required first time only, then it encrypts one data block
(64-bits) per clock cycle. Therefore, the achieved throughput is 35.5 Gbits/s. Full design
schematic and simulation window are shown.(see figure5).
Fig 5: Full DES design schematic generated by Xilinx ISE tool
BLOCKS:1 to 16 (Round Function),17(Initial Permutation),18(Swap),19(Inverse initial
Permutation),20(Key Top),21(Skew Core)
Fig 6: Simulation Window of DES design
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6. PERFORMANCE COMPARISON
The fastest DES software implementation achieves a throughput of 127 Mbit/s on a 300MHz
Alpha 8400 processor[4]. VLSI implementation of DES on static 0.6 micron CMOS technology
[7] is the fastest implementation of DES reported by the literature. The image encryption scheme
was implemented in design with skew and also without skew core key scheduling and the device
utilization details are shown in figure. And it is found that pipelined DES has high speed, high
data throughput and less CLB utilization. The performance analysis in terms of area ,timing and
power was obtained using Synopsys tool.
Fig 7: Various Implementation Results
Fig 8: Orginal ,Encrypted and Decrypted Image
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7. CONCLUSION
This paper describes a high speed, high throughput image scrambling system. A 16-stage
pipelined novel implementation of DES algorithm design is presented here for scrambling. The
input image is split into blocks of 64 bits and it allows the processing of 16 data blocks
simultaneously. Image data blocks can be loaded every clock cycle and after an initial delay of 16
clock cycles the corresponding encrypted/decrypted biomedical image data blocks will appear on
consecutive clock cycles. Different keys can be loaded every clock cycle allowing the possibility
of using multiple keys in any one session of data transfer.
Fig 9: No. of Bits vs No. of Clock Cycles
Fig 10: No. of Bits vs Time
Fig 10: System Clock vs Data Rate
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Author
JInu Elizabeth John:- Completed MTECH VLSI Design from Amrita
University.Currently working as Asst.Professor Electronics and Communication
Engineeing at SaintgitsCollege of Engineering.She has published many papers in
international conferences and journals.Her research areas are
Cryptography,Network Security and Tesing of VLSI Circuits.