A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta Modulator Using Dynamically Biased Op Amp Sharing

1. A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma–Delta
Modulator Using Dynamically Biased Op Amp Sharing
ABSTRACT:
A 2–2 cascaded switched-capacitor sigma-delta modulator is presented for design
of low-voltage, low-power, broadband analog-to-digital conversion. To reduce
power dissipation in both analog and digital circuits and ensure low-voltage
operation, a half-sample delayed-input feed forward architecture is employed in
combination with 4-bit quantization, which results in reduced integrator output
swings and relaxed timing constraint in the feedback path. The integrator power is
further reduced by sharing an op amp in the two integrators in each stage and
periodically changing the op amp bias condition between a high-current and a low-
current mode using a fast low-power high-precision charge pump circuit.
Implemented in a 0.18-μm CMOS technology, the experimental prototype achieves
a 92-dB dynamic range, a 91-dB peak signal-to-noise ratio, and an 84-dB peak
signal-to-noise plus distortion ratio, respectively for a signal bandwidth of 1.25
MHz Operated at a 40-MHz sampling rate, the modulator dissipates 24.3 mW from
a 1 V supply The proposed architecture of this paper analysis the logic size, area
and power consumption using Tanner tool.

2. SOFTWARE IMPLEMENTATION:
 Tanner tool