A 0.1–2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS

1. A 0.1–2-GHz Quadrature Correction Loop for Digital
Multiphase Clock Generation Circuits in 130-nm CMOS
ABSTRACT:
A 100-MHz–2-GHz closed-loop analog in-phase/quadrature correction circuit for
digital clocks is presented. The proposed circuit consists of a phase-locked loop-
type architecture for quadrature error correction. The circuit corrects the phase
error to within a1.5°upto1GHzandtowithin3°at2GHz. It consumes 5.4 mA from a
1.2 V supply at 2 GHz. The circuit was designed in UMC 0.13-µm mixed-mode
CMOS with an active area of 102µm×95µm. The impact of duty cycle distortion
has been analyzed. High-frequency quadrature measurement related issues have
been discussed. The proposed circuit was used in two different applications for
which the functionality has been verified. The proposed architecture of this paper
analysis the logic size, area and power consumption using Tanner tool.
SOFTWARE IMPLEMENTATION:
 Tanner tool