This document discusses the implementation of a matched filter-based direct sequence spread spectrum (DSSS) digital GPS receiver. It describes how a GPS receiver incorporates DSSS techniques to analyze signals from GPS satellites. Specifically, it designs a digital GPS signal receiver in VHDL for an FPGA system on chip application. The receiver takes digital GPS signals and performs C/A code demodulation, despreading, and outputs navigational data bits. It models communication subblocks like C/A code generator, BPSK demodulator, correlator, and threshold detector in VHDL and simulates them. The goal is to model a four channel receiver to process signals from four satellites mixed with additive white Gaussian noise.