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The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
Implementation in OVP
Implementation in OVP: GPP // FOR ALL CORES for (index=0; index<CORES; index++){ ... //////////////////// // BUSES //////////////////// bus[index] = icmNewBus( busName, 32); //////////////////// // PROCESSORS //////////////////// cpu[index] = icmNewProcessor( cpuName, // CPU name "microblaze", // CPU type 0, // CPU cpuId 0, // CPU model flags 32, // address bits microblazeModel, // model file "modelAttrs", // morpher attributes SIM_ATTRS, // attributes cpu_attr, // user-defined attributes microblazeSemihost, // semi-hosting file "modelAttrs" // semi-hosting attributes ); icmConnectProcessorBusses(cpu[index], bus[index], bus[index]); …](https://image.slidesharecdn.com/5-kitpresentationflextilessimulatingenvironmentv1-140908085032-phpapp02/85/FPL-2014-FlexTiles-Workshop-5-FlexTiles-Simulation-Platform-13-320.jpg)
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The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
Implementation in OVP
Implementation in OVP: GPP // FOR ALL CORES for (index=0; index<CORES; index++){ ... //////////////////// // MEMORY //////////////////// localMem[index] = icmNewMemory(memName, 0x7, MICRO_SIZE); icmConnectMemoryToBus( bus[index], "mp1", localMem[index], MICRO_BASE); icmConnectMemoryToBus( bus[index], memportName, shared, SHARE_BASE); if(!icmLoadProcessorMemory(cpu[index], application[index], False, False, True)) return -1; //////////////////// // TIMERS AND INTS //////////////////// timer[index] = icmNewPSE( timerName, // name //timer_path, // model "../Peripherals/Timer/pse.pse", timer_attr, // attrlist 0, // semihost file 0 // semihost symbol ); icmConnectPSEBus( timer[index], bus[index], "plb", 0, TIMER_BASE, (TIMER_BASE+TIMER_SIZE-1)); …](https://image.slidesharecdn.com/5-kitpresentationflextilessimulatingenvironmentv1-140908085032-phpapp02/85/FPL-2014-FlexTiles-Workshop-5-FlexTiles-Simulation-Platform-14-320.jpg)
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The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
Implementation in OVP
Implementation in OVP: GPP // FOR ALL CORES for (index=0; index<CORES; index++){ ... irq[index] = icmNewNet(irqName); icmConnectProcessorNet( cpu[index], irq[index], "Interrupt", ICM_INPUT); icmConnectPSENet( timer[index], irq[index], "Interrupt", ICM_OUTPUT); //////////////////// // UART //////////////////// uartAttr[index] = icmNewAttrList(); icmAddStringAttr(uartAttr[index], "outfile", uartAttrName); uart[index] = icmNewPSE( uartName, // name uart_path, // model uartAttr[index], // attrlist NULL, // semihost file NULL // semihost symbol ); icmConnectPSEBus(uart[index], bus[index], "plb", 0, UART_BASE, (UART_BASE+UART_SIZE-1)); ... }](https://image.slidesharecdn.com/5-kitpresentationflextilessimulatingenvironmentv1-140908085032-phpapp02/85/FPL-2014-FlexTiles-Workshop-5-FlexTiles-Simulation-Platform-15-320.jpg)
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The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
Implementation in OVP
Implementation in OVP: GPP // FOR ALL CORES for (index=0; index<CORES; index++){ ... #ifdef DEBUG if(index==DEBUG_CORE){ cpu[index] = icmNewProcessor( cpuName, // CPU name "microblaze", // CPU type 0, // CPU cpuId 0, // CPU model flags 32, // address bits microblazeModel, // model file "modelAttrs", // morpher attributes ICM_ATTR_DEBUG, // attributes cpu_attr, // user-defined attributes microblazeSemihost, // semi-hosting file "modelAttrs" // semi-hosting attributes ); }else{ #endif ... }](https://image.slidesharecdn.com/5-kitpresentationflextilessimulatingenvironmentv1-140908085032-phpapp02/85/FPL-2014-FlexTiles-Workshop-5-FlexTiles-Simulation-Platform-16-320.jpg)
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The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
Implementation in OVP
Implementation in OVP: Monitoring Core // FOR ALL CORES for (index=0; index<CORES; index++){ ... //connections to central monitoring core; limitation: 16FSL links //Monitor core is last core created, its link is defined by FSL_MONITOR, tile fsl connect to this id and putfsl sends to it //FSL_MONITOR needs to be set to the # of the last core, which equals CORES if(index!=FSL_MONITOR){ char monitorPort[64]; tfsl[index] = icmNewFifo(fsl_ToMonitor_Name, 64, 128); sprintf(monitorPort, "MFSL%d", FSL_MONITOR); icmConnectProcessorConn(cpu[index], tfsl[index], monitorPort, ICM_OUTPUT); ffsl[index] = icmNewFifo(fsl_FromMonitor_Name, 64, 128); sprintf(monitorPort, "SFSL%d", FSL_MONITOR); icmConnectProcessorConn(cpu[index], ffsl[index], monitorPort, ICM_INPUT); } if(CORES==index+1){ char tilePort[64]; for(i=0;i<CORES;i++){ if(i!=FSL_MONITOR){ sprintf(tilePort, "SFSL%d", i); icmConnectProcessorConn(cpu[FSL_MONITOR], tfsl[i], tilePort, ICM_INPUT); sprintf(tilePort, "MFSL%d", i); icmConnectProcessorConn(cpu[FSL_MONITOR], ffsl[i], tilePort, ICM_OUTPUT); } } } ... }](https://image.slidesharecdn.com/5-kitpresentationflextilessimulatingenvironmentv1-140908085032-phpapp02/85/FPL-2014-FlexTiles-Workshop-5-FlexTiles-Simulation-Platform-18-320.jpg)
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The information contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0
Implementation in OVP
Implementation in OVP: DMA-support
Per DMA this is needed:
One CMI: input memory
One CMO: output memory
Adress table:
Local addresses
Remote addresses
GPP
local memory
CMI
CMO
DMA /////////////////////////////// // DMA Peripheral /////////////////////////////// // instantiate the peripheral icmAttrListP config = icmNewAttrList(); icmAddUns64Attr(config, "id", 1); icmPseP dma = icmNewPSE("dma", "../Peripherals/DMA/dma.pse", config, 0, 0); icmConnectPSEBus(dma, bus[2], "slave1", False, mb0_dma0_BASEADDR, mb0_dma0_BASEADDR+7); icmConnectPSEBus(dma, bus[2], "master1", True, 0x00000000, 0xFFFFFFFF); icmConnectPSEBus(dma, bus[0], "slave0", False, mb1_dma0_BASEADDR, mb1_dma0_BASEADDR+7); icmConnectPSEBus(dma, bus[0], "master0", True, 0x00000000, 0xFFFFFFFF);](https://image.slidesharecdn.com/5-kitpresentationflextilessimulatingenvironmentv1-140908085032-phpapp02/85/FPL-2014-FlexTiles-Workshop-5-FlexTiles-Simulation-Platform-20-320.jpg)
Uploaded byFlexTiles Team
FPL'2014 - FlexTiles Workshop - 5 - FlexTiles Simulation Platform
The document outlines the Open Virtual Platforms (OVP) used by the Flextiles project, focusing on high-level simulation, rapid prototyping, and integration of complex software into hardware architecture. Key features include the introduction of the Flextiles platform, its hardware and software components, and the implementation details for various system elements like monitoring cores, DMA support, and accelerator interfaces. It emphasizes the benefits of using OVP for faster simulations and better debugging options in complex, integrated systems.
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FPL'2014 - FlexTiles Workshop - 5 - FlexTiles Simulation Platform
- 1. www.flextiles.eu FlexTiles FlexTilesSimulating Environment based on Open Virtual Platforms (OVP) Stephan Werner (KIT)
- 2. 2 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Outline Outline What is OVP? Why using OVP? Introduction to FlexTiles Platform Implementation in OVP WebGUI Integration in toolchain
- 3. 3 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 What is OVP High-level simulation Trend towards higher levels of abstraction Early Software Evaluation Better Debugging options SystemC TLM SystemC exploring faster simulations Open Virtual Platforms (OVP) Completely new framework Yet designed for good interaction with SystemC Based on binary translation through „morphing“ functions Platform access API and GDB support Peripheral generation
- 4. 4 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Why using OVP Why using OVP: Very complex software in the project OS Management services Resource Managers User applications in Virtual Platforms Hardware not fully integrated Making a cycle-accurate model is not possible Possible: modeling the expected behavior (register set, protocols, etc. Our focus: Rapid Prototyping of complex software Simulation should run as fast as possible Cycle accuracy is not needed OVP is right choice for our application
- 5. 5 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Introduction to the FlexTiles Platform Introduction to the FlexTiles Platform: Hardware GPPs MicroBlazes executing CompOSe One Monitoring Core DSP Icyflex 4 eFPGA Accelerator Interface Virtualizing DSPs and accelerators Network Interfaces Abstraction for different NoCs NoC View in HW: DMAs View in SW: FIFOs
- 6. 6 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Introduction to the FlexTiles Platform: Hardware Homogeneous GPP nodes Heterogeneous accelerators nodes GPP Node AI DSP Node NI GPP Node NI NoC NI NI NI AI AI NI Config. Ctrl. DDR Ctrl. NI GPP Node NI I/O NI Generic Interfaces eFPGA Domain (Reconfigurable HW acc.) Dedicated Accelerator Node Dedicated Accelerator Node
- 7. 7 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Introduction to the FlexTiles Platform Introduction to the FlexTiles Platform: Software CompOSe Real-time OS Guaranteed real-time FIFOs Software view to NoC Cyclo-static dataflow Programming model ELF-bundles Contains information about the different configurations of the CSDF model Contains all executables Virtualization Layer Manages task migration and (re-)distribution Runs as priviledged service
- 8. 8 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Introduction to the FlexTiles Platform: Software
- 9. 9 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Introduction to the FlexTiles Platform: Software Programming Model: CSDF
- 10. 10 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Introduction to the FlexTiles Platform: Software Programming Model: CSDF
- 11. 11 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Implementation in OVP Implementation in OVP: Outline GPPs running the OS The Monitoring Core DMA-support as used for FIFOs Accelerator Interface After implementation: WebGUI Integration in toolflow
- 12. 12 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Implementation in OVP Implementation in OVP: GPP MicroBlaze-model in OVP available Same (cross-compiled) code is executed Timer has to be adapted CompOSe executed Virtualization layer Test environment Can be debugged with GDB NI NoC GPP Core Instruction Cache Local Data Memory Peripherals IT / event iNoC Control Sync Instruction DMA Supervisor
- 13. 13 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Implementation in OVP Implementation in OVP: GPP // FOR ALL CORES for (index=0; index<CORES; index++){ ... //////////////////// // BUSES //////////////////// bus[index] = icmNewBus( busName, 32); //////////////////// // PROCESSORS //////////////////// cpu[index] = icmNewProcessor( cpuName, // CPU name "microblaze", // CPU type 0, // CPU cpuId 0, // CPU model flags 32, // address bits microblazeModel, // model file "modelAttrs", // morpher attributes SIM_ATTRS, // attributes cpu_attr, // user-defined attributes microblazeSemihost, // semi-hosting file "modelAttrs" // semi-hosting attributes ); icmConnectProcessorBusses(cpu[index], bus[index], bus[index]); …
- 14. 14 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Implementation in OVP Implementation in OVP: GPP // FOR ALL CORES for (index=0; index<CORES; index++){ ... //////////////////// // MEMORY //////////////////// localMem[index] = icmNewMemory(memName, 0x7, MICRO_SIZE); icmConnectMemoryToBus( bus[index], "mp1", localMem[index], MICRO_BASE); icmConnectMemoryToBus( bus[index], memportName, shared, SHARE_BASE); if(!icmLoadProcessorMemory(cpu[index], application[index], False, False, True)) return -1; //////////////////// // TIMERS AND INTS //////////////////// timer[index] = icmNewPSE( timerName, // name //timer_path, // model "../Peripherals/Timer/pse.pse", timer_attr, // attrlist 0, // semihost file 0 // semihost symbol ); icmConnectPSEBus( timer[index], bus[index], "plb", 0, TIMER_BASE, (TIMER_BASE+TIMER_SIZE-1)); …
- 15. 15 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Implementation in OVP Implementation in OVP: GPP // FOR ALL CORES for (index=0; index<CORES; index++){ ... irq[index] = icmNewNet(irqName); icmConnectProcessorNet( cpu[index], irq[index], "Interrupt", ICM_INPUT); icmConnectPSENet( timer[index], irq[index], "Interrupt", ICM_OUTPUT); //////////////////// // UART //////////////////// uartAttr[index] = icmNewAttrList(); icmAddStringAttr(uartAttr[index], "outfile", uartAttrName); uart[index] = icmNewPSE( uartName, // name uart_path, // model uartAttr[index], // attrlist NULL, // semihost file NULL // semihost symbol ); icmConnectPSEBus(uart[index], bus[index], "plb", 0, UART_BASE, (UART_BASE+UART_SIZE-1)); ... }
- 16. 16 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Implementation in OVP Implementation in OVP: GPP // FOR ALL CORES for (index=0; index<CORES; index++){ ... #ifdef DEBUG if(index==DEBUG_CORE){ cpu[index] = icmNewProcessor( cpuName, // CPU name "microblaze", // CPU type 0, // CPU cpuId 0, // CPU model flags 32, // address bits microblazeModel, // model file "modelAttrs", // morpher attributes ICM_ATTR_DEBUG, // attributes cpu_attr, // user-defined attributes microblazeSemihost, // semi-hosting file "modelAttrs" // semi-hosting attributes ); }else{ #endif ... }
- 17. 17 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Implementation in OVP Implementation in OVP: Monitoring Core Not every GPP can have an UART Hardware limited Monitoring Core gathers the output Only GPP with I/O Connected via FSL to other GPPs On OVP: UART On board: Ethernet to PC Same operations run in OVP and on board getfsl, putfsl CompOSeCompOSeMonitoringCoreCompOSeUART(OVP) (Board)
- 18. 18 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Implementation in OVP Implementation in OVP: Monitoring Core // FOR ALL CORES for (index=0; index<CORES; index++){ ... //connections to central monitoring core; limitation: 16FSL links //Monitor core is last core created, its link is defined by FSL_MONITOR, tile fsl connect to this id and putfsl sends to it //FSL_MONITOR needs to be set to the # of the last core, which equals CORES if(index!=FSL_MONITOR){ char monitorPort[64]; tfsl[index] = icmNewFifo(fsl_ToMonitor_Name, 64, 128); sprintf(monitorPort, "MFSL%d", FSL_MONITOR); icmConnectProcessorConn(cpu[index], tfsl[index], monitorPort, ICM_OUTPUT); ffsl[index] = icmNewFifo(fsl_FromMonitor_Name, 64, 128); sprintf(monitorPort, "SFSL%d", FSL_MONITOR); icmConnectProcessorConn(cpu[index], ffsl[index], monitorPort, ICM_INPUT); } if(CORES==index+1){ char tilePort[64]; for(i=0;i<CORES;i++){ if(i!=FSL_MONITOR){ sprintf(tilePort, "SFSL%d", i); icmConnectProcessorConn(cpu[FSL_MONITOR], tfsl[i], tilePort, ICM_INPUT); sprintf(tilePort, "MFSL%d", i); icmConnectProcessorConn(cpu[FSL_MONITOR], ffsl[i], tilePort, ICM_OUTPUT); } } } ... }
- 19. 19 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Implementation in OVP Implementation in OVP: DMA-support
- 20. 20 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Implementation in OVP Implementation in OVP: DMA-support Per DMA this is needed: One CMI: input memory One CMO: output memory Adress table: Local addresses Remote addresses GPP local memory CMI CMO DMA /////////////////////////////// // DMA Peripheral /////////////////////////////// // instantiate the peripheral icmAttrListP config = icmNewAttrList(); icmAddUns64Attr(config, "id", 1); icmPseP dma = icmNewPSE("dma", "../Peripherals/DMA/dma.pse", config, 0, 0); icmConnectPSEBus(dma, bus[2], "slave1", False, mb0_dma0_BASEADDR, mb0_dma0_BASEADDR+7); icmConnectPSEBus(dma, bus[2], "master1", True, 0x00000000, 0xFFFFFFFF); icmConnectPSEBus(dma, bus[0], "slave0", False, mb1_dma0_BASEADDR, mb1_dma0_BASEADDR+7); icmConnectPSEBus(dma, bus[0], "master0", True, 0x00000000, 0xFFFFFFFF);
- 21. 21 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Implementation in OVP Implementation in OVP: Accelerator Interface NI NoC Output Data DMA DMA data out req FIFO Input Data DMA DMA data in req FIFO data rd ctrl wr Accelerator Output Ch. Input Ch. data wr ctrl wr Input Config DMA DMA cfg req FIFO Config.Ch. config wr config wr config rd ctrl wr Work req FIFO ctrl wr ctrl rd control write / status read Synchronization / Notification read . write notification config wr send sync Control / Status Channel mem ctrl mem ctrl Debug Ch. write / read debug notification read
- 22. 22 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Implementation in OVP Implementation in OVP: Accelerator Interface EXPLANATION IN COMBINATION WITH LIVE- PRESENTATION OF CODE
- 23. 23 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Implementation in OVP Implementation in OVP: Accelerator Interface AI implemented as peripheral in OVP Runs seperately from GPP simulation Algorithm of accelerator is executed on host natively Fast simulation Can be used as template for accelerators Insert algorithm in function start_calc()
- 24. 24 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Usability WebGUI Generation of Hardware-Architecture
- 25. 25 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Usability WebGUI Application-Binding
- 26. 26 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Usability WebGUI Simulation in WebGUI
- 27. 27 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Integration in toolchain Integration in toolchain
- 28. 28 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Integration in toolchain Integration in toolchain
- 29. 29 / Theinformation contained in this document and any attachments are the property of FlexTiles consortium. You are hereby notified that any review, dissemination, distribution, copying or otherwise use of this document must be done in accordance with the CA of the project (TRT/DJ/624412785.2011). Template version 1.0 Implementation in OVP Thank you for your attention Questions ?