A deep dive into energy efficient multi core processor

1. A Deep Dive into Energy Efficient Multi-
core Processor
Speaker：呂宗螢
Adviser：梁文耀 老師
Date：2006/11/1

2. 嵌入式及平行系統實驗室
Hardware Software Cooperation for Best
Performance-Power Optimization
 ACPI
 Schedule appropriate idle
state, either C1, C2, ….Cn
 OS schedule and decide
designated idle state
 Execute BIOS code
sequence
 Enter idle state and
periodically re-evaluate
 Quickly back to active
state when the break
event occurs
 Utilize idle state effectively

3. 嵌入式及平行系統實驗室
Power States
 C0 is core active power state
 C1 is auto halt state
 Instruction execution halted
 Core clock is off
 Quick transition and switch on/off almost immediately
 C2 is stop clock state
 Core and bus clock off
 The front side bus can placed in a lower power state
 Chipset can initiate power-saving measure
 C3 is deep sleep state
 Clock generator off
 Processor disables internal Phase Locked Loops
 C4 is deeper sleep state
 Reduce VCC
 DC4 is further deeper sleep state
 Further reduce VCC
 DC4 has eliminating most static power but taking a
long time the enter DC4 and back to C0

4. 嵌入式及平行系統實驗室
Multi-core Power States
 Multi-core power state
 Each core has its own power state
 Multi-core shared resource has power states for all cores
• Maximum performance benefit
• Minimum power consumption
 Multi-core power control partion
 Typical individual core units：execution units , core scheduler, L1 cache, core
clocking control
 Typical shared resources：APIC, global power control, L2 cache, bus

5. 嵌入式及平行系統實驗室
Intel Core™ 2 Duo Processor
 A core reduce the frequency , the other
core still runt at full speed
 Three domain
 Each core have power management
domain
 Share reources a power management
domain
 All domain share a single power plane
and a single-core PLL(Phase Locked
Loops)
 The Coordination mechanism serves as a
transparent layer between the individuall
controlled cores and the shared resource
on die and on the platform
 Determines the required CPU C-state
 Base on both cores’ individual requests
 Controls the state of the shared
resources

6. 嵌入式及平行系統實驗室
Smart Cache Optimization
 Smart Cache size shrink
 Less accesses than threshold
 Multi-core condition permits
 Stop cach size shrink
 Other core active
 Not meet multi-core shrinking
condition
 Interrupt pending
 Expand cache size
 Access frequency over threshold
 Other core sleep state change
 Multi-core trend to active