The document describes a research project called FlexTiles that aims to develop a new type of heterogeneous manycore chip with self-adaptive capabilities. The chip will use a novel embedded field-programmable gate array (eFPGA) technology that allows seamless relocation and migration of processes at runtime to optimize performance and power consumption. The project involves 8 partners across 5 countries and has a budget of 3.67 million euros over 3 years. The goals are to address increasing application dynamicity, improve software development productivity, and increase energy efficiency for embedded systems.

1. www.thalesgroup.com
FP7 project
Fabrice Lemonnier, Hipeac 2012
Research & Technology

2. 2 /
Cognitive radio
Smart camera
Reduction of Time To Market
Increase of resilience to faults
interactive to their environment
Reduction of power consumption
Rapid adaptation for a product line
Drone
Products are more and more adaptive, dynamic and
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Industrial issues
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3. 3 / Challenges
Challenge 1: To address the steadily increasing
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application dynamicity using self-adaptive capabilities.
Challenge 2: To increase the software development
productivity of manycore for Time to Market and cost
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reasons and to enable the reuse of legacy software and
hardware codes.
Challenge 3: To increase accessibility to manycore
technologies and propose a European alternative on the
worldwide market of this technology.
Challenge 4: To increase energy efficiency for embedded
systems and High-Performance Computing (HPC) systems.

4. 4 / Objectives of the project
Objective 1: To raise the programming efficiency of
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heterogeneous manycores.
Objective 2: To develop a dynamic reconfigurable
technology with pre-emption and relocation capabilities.
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Objective 3: To enable self-adaptation with a virtualisation
layer.
Objective 4: To develop a heterogeneous manycore based
on available IPs: definition of generic interfaces.

5. 5 / State of art
Existing manycores provide static allocation
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and sheduling
• TILE-Gx™ 8000 from Tilera (16 to 100 cores)
MPPA® from Kalray (256 to 1024 cores)
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•
• PicoArray from Picochip (248 cores)
Projects:
without reconfigurable technology with reconfigurable technology
Programmability
FlexTiles
Tsar Mosart ADAM
Morpheus Apple-Core
Aether
ReconOS
FOSFOR (ANR)
Hardware Flexibility / dynamicity

6. 6 /
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on available IPs: definition of generic interfaces
Objective 1: To develop a heterogeneous manycore based
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7. generation generation 7 /
Code Bitstream
Virtual Virtual
Virtualisation Layer
Kernel
& Allocation
Resource Monitoring
NoC
data
control
Tile Tile Tile
Tile Tile Tile
I
N
Tile
Reconfigurable area
LMEM
DMU
Tile core : generic part
GPP
Internal communication resource
I
I
A
A
G
G
area
specific part
function
Tile accelerators :
dedicated
reconfigurable
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on available IPs: definition of generic interfaces
Objective 1: To develop a heterogeneous manycore based
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8. 8 / Objective 2: To raise the programming efficiency of
heterogeneous manycores
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Application
Parallelisation, partioning
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Compilation Synthesis, P&R
The toolchain
reloadable binary code reloadable bitstream
Operating Library API
ACTION
Virtualisation layer
The operating
library Kernel
Resource MONITORING DIAGNOSIS
Monitorin & Allocation O = F(L)
SYSTEM
Hardware Abstraction Layer API
The heterogenous Hardware Abstraction Layer
multicore
Hardware Tile

9. 9 / Objective 3: To enable self-adaptation with a virtualisation
layer
ACTION
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MONITORING DIAGNOSIS
O = F(L)
SYSTEM
I/O
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Accelerator/Virtual Code
GPP I DMA GPP I DMA GPP I DMA
N N N
O O O
LMEM C LMEM C DSP LMEM C
I/O REC
GPP I DMA GPP I DMA GPP I DMA
N N N Run-time
O O O allocation / binding
LMEM C REC LMEM C LMEM C REC
DSP
GPP I DMA GPP I DMA GPP I DMA
N N N
O O O
LMEM C REC LMEM C LMEM C
DDR DSP
Noc
DDR

10. 10 /
NoC
Homogeneous manycore
3D stacked reconfigurable layer
Tile
Tile
Tile
Tile
Tile
Tile
Tile
FlexTiles: a 3D stack chip
Tile
Tile
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technology with pre-emption and relocation capabilities
Objective 4: To develop a new dynamic reconfigurable
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11. 11 / Tool flow
Application
(C code)
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Graphic C to SpearDE
input representation
(manual) Conversion (Cosy)
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architecture Data parallelisation
representation Mapping (SpearDE)
Streaming optimisation
(Cosy)
Compilation (Cosy) Catapult
Virtual executable code P&R
running on manycore
layer
Virtual bitstream
generator
Virtual bitstream running
on eFPGA layer

12. 12 / Parallelisation and mapping of an application
thread1
thread3 thread1 thread2thread2 thread4
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API
I/O Acc1 Acc1 Acc3 Acc4 DDR ctrl
Tile Tile Tile Tile Tile Tile
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NoC
Dynamic allocation
Dynamic allocation
I/O
Acc1 thread1 thread2
Acc3
thread1 thread2 thread3 thread4
Acc1
Acc4 API
Tools for parallelisation
Tools for parallelisation and mapping
and mapping
Application

13. 13 / Results
Heterogeneous manycore with self adaptive capabilities
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• Heterogeneous manycore
• Reconfigurable technology with relocation and migration capabilities; virtual
bitstream
• Virtualisation layer to provide an abstraction of the heterogeneous manycore
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and self adaptive services
• Feasability study of 3D stacking with a dedicated layer to reconfigurable
technology above the manycore layer
• Tools chain for parallelisation and compilation
Deliverables :
• SystemC simulator and FPGA demonstrators for the
heterogeneous manycore architecture
• Physical design results for embedded reconfigurable technology
on a layer of 3D stacking
• Virtualisation layer code, kernel
• Tool chain code

14. 14 /
Duration: 36 months
8 partners in 5 countries
Starting date: 15/10/2011
Website: www.flextiles.eu
Funding budget: 3,670,000€
Project coordinator: THALES
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FlexTiles in few words
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15. 15 / Consortium
Partners & Third Country Main scientific and
Party technical contributions
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THALES France Infrastructure and
applications
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KIT Germany Virtualisation layer
TUE Netherlands Kernel ; NoC
CSEM Switzerland DSP
CEA France NoC ; 3D stacking
UR1 France Reconfigurable technology
SUNDANCE United FPGA Demonstrator
Kingdom
ACE Netherlands Parallelisation and
compilation Tools

16. 16 / Conclusion and perspectives
•The main objective of the FlexTiles project is to define a
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new type of manycore providing a breakthrough in terms
of self adaptivity.
•Thishigh flexibility will be based on a new eFPGA
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technology providing seamless relocation and migration
•Re-location will be done at runtime to obtain the best
trade off between performance and power consumption
•We will propose a solution for the programming issue of
the manycores chip.
Perpectives: definition of the platform specifications with
keeping homogeneous approach from the programming
model to the architecture definition.

17. 17 /
Questions ??
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