- Thales proposes FlexTiles, a heterogeneous manycore chip architecture with self-adaptive capabilities. - FlexTiles aims to address the challenges of increasing application dynamicity, software development productivity for manycore, and reuse of legacy software and hardware IPs. - It combines an FPGA layer, manycore layer, and 3D stacked chip design to enable dynamic adaptation to the environment through runtime reconfiguration and resource management.

1. www.thalesgroup.com
FlexTiles:
Heterogeneous Manycore with Self Adaptive Capabilities
Fall school 2012
Fabrice Lemonnier, 2nd of October, 2012
Research & Technology

2. 2 /
low volume
Cognitive radio
low power consumption
Embedded Real-Time Applications
Smart camera
UAV
Fault-tolerance
Time To Market
adaptable product line
Adapt to environment  dynamicity, flexibility & dependability
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Industrial issues
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3. 3 / Challenges
address increasing application increase software development
dynamicity productivity of manycore
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-using self-adaptive capabilities -reduce Time to Market
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-reuse of legacy software
-reuse of hardware IPs.
increase accessibility to increase energy efficiency
manycore technologies
-for embedded systems
-propose a European alternative on
the worldwide market of this -andHigh-Performance Computing
technology (HPC) systems.

4. 4 / Manycore: main issue for industry
 Programmability:
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 Time to market
 Development cost
 Reuse of legacy software
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Why take so many risks with manycore ?
Most of industrials want to continue
like the past few years: compile without
thinking (as much as possible) !
No more Free lunch ! In the near future
the processors will all be made of multi-cores and many-
cores.
Nevertheless, can we provide solutions to ease the
programmation ?

5. 5 /
•
•
A FPGA layer
A manycore layer
A 3D stacked chip based on:
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Our proposition
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6. 6 / Self adaptive capabilities, why?
•Tobe able to dynamically adapt the architecture to the
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current request of the application for the same power
consumption
•Evolutionof the technology: reduction of the reliability
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and the yield of current and future sub-micron
technologies -> adaptation depending on the faulty cores.
•Increase energy efficiency
•Increasethe programming efficiency by taking a part of
the mapping complexity at runtime
•Temperature management -> adaptation of the
application mapping

7. 7 / Objectives of the project
1) develop a heterogeneous manycore based on available IPs
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definition of generic interfaces
2) improve programming efficiency of heterogeneous
manycores
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3) self-adaptation
thanks to virtualisation layer
4) develop a dynamic reconfigurable technology
pre-emption and relocation capabilities.

8. 8 /
•
•
•
•
P2012 from STM
allocation and sheduling
PicoArray from Picochip (248 cores)
MPPA® from Kalray (256 to 1024 cores)
TILE-Gx™ 8000 from Tilera (16 to 100 cores)
Existing manycores are only compliant with static
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Existing solutions
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9. 9 /
•
•
•Main
•FOSFOR
Projects:
•Morpheus
drawbacks:
multicore on FPGA
the scalability of the solution
the limitation of the size of the FPGA area
technologies managed by an ARM processor.
(ANR project): distributed OS for heterogeneous
(FP6 project): heterogeneous chip with 3 FPGA
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Research projects
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10. 10 /
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otherwise use of this document is strictly prohibited without Thales prior written approval. ©THALES 2011. Template trtp version 7.0.8

11. 11 /
Model of Computation
Optimisation tools
Model of Execution
Model of programmation
Common Interfaces
strategies of relocation
Flexible Hardware
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Holistic Approach
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12. 12 /
GPP
DSP nodes
eFPGA nodes
Slave Nodes
Master Nodes
Master-slave execution model
data
DMA
requests
DMA
NI
NI
NoC
GPP Node
control
/ status
node
accelerator
acc
requests
Accelerator Interface (AI)
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Programming efficiency: common execution model
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13. 13 /
MoC
•Optimisation and parallelisation tools can only
be used on static applications.
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•Necessity to identify static clusters inside the
applications based on SDF/CSDF MoC
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Act Act
SDF, CSDF MoC Act Act
Act : Actor
Act
: static cluster
Act Act Act : Clusters group managed
by one state management
: Cluster group input/output
actor: consume and produce token of data with : Cluster input/output
predefined and static rules

14. 14 / Tool flow
The Tool flow is based on Application
(C code)
2 main tools:
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•Thales tool: SpearDE
Graphic C to SpearDE
•ACE tool: Cosy input representation
(manual) Conversion (Cosy)
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Data
architecture parallelisation
representation Mapping
(SpearDE)
Streaming
optimisation
(Cosy)
Compilation
(Cosy)
Library of IPs
executable code
Slave cores Master cores

15. 15 / Dynamic relocation
thread1
thread3 thread1 thread2thread2 thread4
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API
I/O Acc1 Acc1 Acc3 Acc4 DDR ctrl
GPP GPP GPP GPP GPP GPP
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NoC
runtime
Dynamic relocation
compile time
I/O
Acc1 thread1 thread2
Acc3
thread1 thread2 thread3 thread4
Acc1
Acc4 API
Tools for Tools for
parallelisation parallelisation
and mapping and mapping
Application

16. 16 /
Model of Computation
Optimisation tools
Model of Execution
Model of programmation
Common Interfaces
strategies of relocation
Flexible Hardware
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Holistic Approach
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17. 17 /
nodes
Generic
Interfaces
accelerators
GPP nodes
Heterogeneous
Homogeneous
AI
NI
NI
DSP
Node
GPP Node
AI
NI
NI
Node
GPP Node
Dedicated
Accelerator
HW acc.)
NoC
AI
NI
NI
Node
GPP Node
Dedicated
Accelerator
eFPGA Domain (Reconfigurable
NI
DDR Ctrl.
NI
NI
I/O
Config. Ctrl.
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Modularity and scalability: common interfaces
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18. 18 /
event
Act
Act
Act
Act
Act
states management
Act
Act
state 2
state 1
Act
state 3
cluster group
Act
: Actor
: static cluster
: Cluster input/output
: Cluster group input/output
: Clusters group managed
by one state management
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Dynamicity: the cluster group
otherwise use of this document is strictly prohibited without Thales prior written approval. ©THALES 2011. Template trtp version 7.0.8

19. 19 / Dynamicity at cluster group level
event cluster group 1 event cluster group 4
states management event cluster group 3 states management
states management state 1
The information contained in this document and any attachments are the property of THALES. You are hereby notified that any review, dissemination, distribution, copying or
state 1
state 1 Act Act
nop
Act Act Act
sensor
data
Act Act
otherwise use of this document is strictly prohibited without Thales prior written approval. ©THALES 2011. Template trtp version 7.0.8
event cluster group 5
states management
state 1
event cluster group 2
states management Act Act Act
s Act Act
c g
sensor a state 1.1 a
data Act : Actor
state 2 t Act Act t
Act
t h
Act Act Act
e e : static cluster
Act Act
r r
Act Act : Clusters group managed
state 1.2 by one state management
Act Act Act : Cluster group input/output
: Cluster input/output
Act Act

20. 20 / Start a new part of the application
event cluster group 1 event cluster group 4
states management event cluster group 3 states management
states management state 1
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state 1 Act Act
Act Act Act
sensor
data state 2
Act Act
otherwise use of this document is strictly prohibited without Thales prior written approval. ©THALES 2011. Template trtp version 7.0.8
Act Act Act
Act event cluster group 5
states management
state 1
event cluster group 2
states management Act Act Act
s Act Act
c g
sensor a state 1.1 a
data Act : Actor
state 2 t Act Act t
Act
t h
Act Act Act
e e : static cluster
Act Act
r r
Act Act : Clusters group managed
state 1.2 by one state management
Act Act Act : Cluster group input/output
: Cluster input/output
Act Act

21. 21 / Modification of the behaviour
event cluster group 1 event cluster group 4
states management event cluster group 3 states management
states management
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state 1
Act Act Act
sensor state 2
data state 2
Act Act Act
Act
otherwise use of this document is strictly prohibited without Thales prior written approval. ©THALES 2011. Template trtp version 7.0.8
Act Act Act
Act
Act event cluster group 5
states management
state 1
event cluster group 2
states management Act Act Act
s Act Act
c g
sensor a state 1.1 a
data Act : Actor
state 2 t Act Act t
Act
t h
Act Act Act
e e : static cluster
Act Act
r r
Act Act : Clusters group managed
state 1.2 by one state management
Act Act Act : Cluster group input/output
: Cluster input/output
Act Act

22. 22 / Modification of the parallelisation level
event cluster group 1 event cluster group 4
states management event cluster group 3 states management
states management
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state 1
Act Act Act
sensor state 2
data state 2
Act Act Act
Act
otherwise use of this document is strictly prohibited without Thales prior written approval. ©THALES 2011. Template trtp version 7.0.8
Act Act Act
Act
Act event cluster group 5
states management
state 1
event cluster group 2
states management Act Act Act
s Act Act
c g
sensor a a
data Act : Actor
state 2 t t
t h
Act Act Act
e e : static cluster
r r
Act Act : Clusters group managed
by one state management
: Cluster group input/output
: Cluster input/output

23. 23 /
A1.4
A1.3
A1.2
A1.1
relocation
A2.4
A2.3
A2.2
A2.1
•FPGA
A3
A4
A5
•FPGA
•GPP
cluster1p1
A1.4
A1.3
A1.2
A1.1
relocation
A2.4
A2.3
A2.2
A2.1
•DSP
A3
A4
A5
•DSP
•GPP
cluster1p1
A1.4
A1.3
A1.2
A1.1
relocation
A2.4
A2.3
A2.2
A2.1
•DSP
A3
A4
A5
•DSP
•DSP
time
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Dynamicity at cluster level
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cluster1p1

24. 24 /
A Virtualisation Layer for self adaptive capabilities
Virtualisation services provide a high level of abstraction of the heterogeneous
resources: communication and accelerators management
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Self adaptive services define actions to be taken depending on events (monitoring):
relocation, DVFS,…
Allocation file Application
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Self adaptive services
ACTION
Virtualisation Virtualisation
Layer services
MONITORING DIAGNOSIS
O = F(L)
SYSTEM
kernel Monitoring Actuators
Task Memory Network Communication
Scheduler
Cluster Semaphore
mngt mngt services management mngt event mngt

25. AI
NI
NI
25 /
DSP
Node
GPP Node
AI
NI
NI
Node
GPP Node
Dedicated
Accelerator
NoC
AI
NI
NI
Node
GPP Node
Dedicated
Accelerator
NI
DDR Ctrl.
NI
Config. Ctrl.
eFPGA Domain (Reconfigurable HW acc.)
NI
I/O
Accelerator/Virtual Code
Mapping
MONITORING
ACTION
SYSTEM
O = F(L)
DIAGNOSIS
Dynamic
allocation / binding
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Self-adaptation
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26. 26 /
NoC
Homogeneous manycore
Tile
Tile
Tile
Tile
Tile
Tile
Tile
FlexTiles: a 3D stack chip
Tile
Tile
3D stacked reconfigurable layer
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New dynamic reconfigurable technology
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27. 27 /
NoC
Homogeneous manycore
3D stacked reconfigurable layer
Tile
Tile
Tile
Tile
Tile
Tile
Tile
Map Accelerated functions
FlexTiles: a 3D stack chip
Tile
Tile
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New dynamic reconfigurable technology
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28. 28 /
NoC
Homogeneous manycore
3D stacked reconfigurable layer
Tile
Tile
Tile
Duplicate
Tile
Tile
Tile
Tile
FlexTiles: a 3D stack chip
Tile
Tile
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New dynamic reconfigurable technology
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29. 29 /
NoC
Homogeneous manycore
3D stacked reconfigurable layer
Tile
Tile
Tile
Migrate
Tile
Tile
Tile
Tile
FlexTiles: a 3D stack chip
Tile
Tile
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New dynamic reconfigurable technology
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30. 30 /
GPP
shMEM
on chip
icache
dcache
dLMEM GPP
NI
DSP
iLMEM DSP
dLMEM DSP
NI
data
NOC
NOC
NOC
NOC
NOC
control
bitstream
test/debug
instruction
eFPGA
iLMEM eFPGA
dLMEM eFPGA
NI
+
NI
ctrl
DDR
chip
DDR
NoC QoS
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31. 31 / Conclusion
Parallelisation is the only way to reach HPC for low power
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consumption.
But parallelisation is not enough, customisation is also
necessary
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 Only affordable for high volumes
Reconfigurable customisation is the solution:
 Increase accessibility to heterogeneous manycore technology
 Offers self-adaptive capabilities

32. 32 /
Duration: 36 months
Starting date: 15/10/2011
Funding budget: 3,670,000€
Project coordinator: THALES
FlexTiles
www.flextiles.eu
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FlexTiles: FP7 project
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33. 33 / 8 partners in 5 countries Consortium and questions
Partners & Third Country Main scientific and
Party technical contributions
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THALES France Infrastructure and
applications
KIT Germany Virtualisation layer
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TUE Netherlands Kernel ; NoC
CSEM Switzerland DSP
CEA France NoC ; 3D stacking
UR1 France Reconfigurable technology
SUNDANCE United FPGA Demonstrator
Kingdom
ACE Netherlands Parallelisation and
compilation Tools

34. 34 /
With FlexTiles, Industry will be able to…
Take the plunge into the manycore world !
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35. 35 /
Questions ?
Thank you for your attention
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