Network analysis and synthesis question and answer...Manash Deka
Here is a upload of a set of short questions and answers from the subject Network Analysis and Synthesis mainly necessary for Electrical Engineering and Electronics Engineering.
We know that electric motor is a machine that converts electrical energy into mechanical energy. But there difference between conventional motor and stepper motor.
1. Input to stepper motor is in the form of electric pulses whereas input to conventional motor is from constant voltage source
2. A CM has a free running shaft whereas shaft of SM moves through angular steps.
So this presentation will help to understand the basic operating principal of stepper motor, its types and some applications
Network analysis and synthesis question and answer...Manash Deka
Here is a upload of a set of short questions and answers from the subject Network Analysis and Synthesis mainly necessary for Electrical Engineering and Electronics Engineering.
We know that electric motor is a machine that converts electrical energy into mechanical energy. But there difference between conventional motor and stepper motor.
1. Input to stepper motor is in the form of electric pulses whereas input to conventional motor is from constant voltage source
2. A CM has a free running shaft whereas shaft of SM moves through angular steps.
So this presentation will help to understand the basic operating principal of stepper motor, its types and some applications
Chopper basically uses a Thyristor for high power applications. The process of turning off a conducting Thyristor is known as commutation. Here Thyristor is turned off by a current pulse that is why it is called a Current Commutated Chopper.
The performance obtainable from a single-stage amplifier is often insufficient for many applications, hence several stages may be combined forming a multistage amplifier. These stages are connected in cascade, i.e. output of the first stage is connected to form input of second stage, whose output becomes input of third stage, and so on.
thank u
Hansraj MEENA
Chopper basically uses a Thyristor for high power applications. The process of turning off a conducting Thyristor is known as commutation. Here Thyristor is turned off by a current pulse that is why it is called a Current Commutated Chopper.
The performance obtainable from a single-stage amplifier is often insufficient for many applications, hence several stages may be combined forming a multistage amplifier. These stages are connected in cascade, i.e. output of the first stage is connected to form input of second stage, whose output becomes input of third stage, and so on.
thank u
Hansraj MEENA
HEAP SORT ILLUSTRATED WITH HEAPIFY, BUILD HEAP FOR DYNAMIC ARRAYS.
Heap sort is a comparison-based sorting technique based on Binary Heap data structure. It is similar to the selection sort where we first find the minimum element and place the minimum element at the beginning. Repeat the same process for the remaining elements.
ACEP Magazine edition 4th launched on 05.06.2024Rahul
This document provides information about the third edition of the magazine "Sthapatya" published by the Association of Civil Engineers (Practicing) Aurangabad. It includes messages from current and past presidents of ACEP, memories and photos from past ACEP events, information on life time achievement awards given by ACEP, and a technical article on concrete maintenance, repairs and strengthening. The document highlights activities of ACEP and provides a technical educational article for members.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Low power architecture of logic gates using adiabatic techniquesnooriasukmaningtyas
The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.
