2016 IEEE VLSI TITES FROM MSR PROJECTS-9581464142

MSR PROJECTS
(PLC & MATLAB Training
IEEE/LIVE PROJECTS for B.TECH/M.TECH)
Address: #213B,Nilagiri Block,Adhithya Enclave, Ameerpet, HYDERABAD-
38.EMail: msrprojectshyd@gmail.com, www.msrprojectshyd.com
Web: http://msrprojects.weebly.com facebook.com/m.s.r.project, No: +91 9581464142.
VERY LARGE SCALE INTEGRATION (VLSI)
S.NO TECHNO
LOGY
TITLE NAME YEAR
1 FRONT
END
.Pre-Encoded Multipliers Based on Non-
Redundant Radix-4 Signed-Digit Encoding
2016
2 FRONT
END
Floating-Point Butterfly Architecture Based on
Binary Signed-Digit Representation
2016
3 FRONT
END
Flexible DSP Accelerator Architecture
Exploiting Carry-Save Arithmetic
2016
4 FRONT
END
.A High-Performance FIR Filter Architecture for
Fixed and Reconfigurable Applications
2016
5 FRONT
END
A Method to Design Single Error Correction
Codes With Fast Decoding for a Subset of
Critical Bits
2016
6 FRONT
END
On Efficient Retiming of Fixed-Point Circuits 2016
7 FRONT
END
Concept, Design, and Implementation of
Reconfigurable CORDIC
2016
8 FRONT
END
Fault Tolerant Parallel FFTs Using Error
Correction Codes and Parseval Checks
2016
9 FRONT
END
Low-Power Parallel Chien Search Architecture
Using a Two-Step Approach
2016
10 FRONT
END
An Efficient Single and Double-Adjacent Error
Correcting Parallel Decoder for the (24,12)
Extended Golay Code
2016
11 FRONT
END
Memory-Reduced Turbo Decoding Architecture
Using NII Metric Compression
2016
12 FRONT
END
Multiple Constant Multiplication Algorithm for
High-Speed and Low-Power Design
2016
13 FRONT Design and Analysis of Inexact2016 Floating- 2016

MSR PROJECTS
END Point Adders
14 FRONT
END
A Mixed-Decimation MDF Architecture for
Radix-2k Parallel FFT
2016
15 FRONT
END
A Modified Partial Product Generator for
Redundant Binary Multipliers
2016
16 FRONT
END
A Cellular Network Architecture With
Polynomial Weight Functions
2016
17 FRONT
END
.A Normal I/O Order Radix-2 FFT Architecture
to Process Twin Data Streams for MIMO
2016
18 FRONT
END
High Speed Hybrid Double Multiplication
Architectures Using New Serial-Out Bit- Level
Mastrovito Multipliers
2016
19 FRONT
END
Low-Cost High-Performance VLSI Architecture
for Montgomery Modular Multiplication
2016
20 FRONT
END
A High-Speed FPGA Implementation of an RSD-
Based ECC Processor
2016
21 FRONT
END
VLSI Design for Convolutive Blind Source
Separation
2016
22 FRONT
END
High-Speedand Energy-Efficient Carry Skip
Adder Operating Under a Wide Rangeof Supply
Voltage Levels
2016
23 FRONT
END
Input-Based Dynamic Reconfiguration of
Approximate Arithmetic Units for Video
Encoding
2016
24 FRONT
END
Hardware and Energy-Efficient Stochastic LU
Decomposition Scheme for MIMO Receivers
2016
25 FRONT
END
Hybrid LUT/Multiplexer FPGA Logic
Architectures
2016
26 FRONT
END
Performance/Power Space Exploration for
Binary64 Division Units
2016

MSR PROJECTS
27 FRONT
END
A High Throughput List Decoder Architecture
for Polar Codes
2016
28 FRONT
END
A Novel Coding Scheme for Secure
Communications in Distributed RFID Systems
2016
29 FRONT
END
Arithmetic algorithms for extended precision
using floating point expansions
2016
30 FRONT
END
Digital Multiplierless Realization of Two-
Coupled Biological Hindmarsh–Rose Neuron
Model
2016
31 BACK
END
A Low Power Trainable Neuromorphic
Integrated Circuit That Is Tolerant to Device
Mismatch
2016
32 BACK
END
A 55-GHz-Bandwidth Track-and-Hold
Amplifier in 28-nm Low-Power CMOS
2016
33 BACK
END
A Low-Power Incremental Delta–Sigma ADC
for CMOS Image Sensors
2016
34 BACK
END
Low-Power ASK Detector for Low Modulation
Indexes and Rail-to-Rail Input Range
2016
35 BACK
END
. A Low-Power Robust Easily Cascaded
PentaMTJ-Based Combinational and Sequential
Circuits
2016
36 BACK
END
PNS-FCR: Flexible Charge Recycling Dynamic
Circuit Technique for Low-Power
Microprocessors
2016

MSR PROJECTS
37 BACK
END
Low-Power Variation-Tolerant Nonvolatile
Lookup Table Design
2016
38 BACK
END
Dual Use of Power Lines for Design-for-
Testability—A CMOS Receiver Design
2016
39 BACK
END
One-Cycle Correction of Timing Errors in
Pipelines With Standard Clocked Elements
2016
40 BACK
END
 High performance VLSI architecture for 2-D
DWT using lifting scheme
2016
2016 IEEE:
1 .A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number
System
2. Area-Delay-Power-Aware Adder Placement Method for RNS Reverse Converter
Design
3. Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores
for FPGAs
4. Logic Synthesis in Reversible PLA
5. Low complexity and area efficient reconfigurable multimode inter leaver
address generator for multi standard radios
6. Floating-Point Butterfly Architecture Based on Binary Signed Digit
Representation
7. Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and
Reliability of Embedded Memories

MSR PROJECTS
8. Low-Cost and High-Reduction Approaches for Power Droop During Launch-
On-Shift Scan-Based Logic BIST
9. Computing Seeds for LFSR-Based Test Generation From Non test Cubes
10. Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units
11. Hardware Architectural Support for Caching Partitioned Reconfigurations in
Reconfigurable Systems
12. Design of adder and subtractor circuits in majority logic-based field-coupled
QCA Nano computing
13. Design of Efficient BCD Adders in Quantum Dot Cellular Automata
14. Design and simulation of single layered Logic Generator Block using Quantum
Dot Cellular Automata
15. Design and Analysis of Digital Circuits Using QCA Logic
16. Design and simulation of Turbo encoder in quantum-dot cellular automata
17. A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis
18. A New XOR-Free Approach for Implementation of Convolutional Encoder
19. Optimizing the Implementation of SEC–DAEC Codes in FPGAs
20. A New Fast and Area-Efficient Adder-Based Sign Detector for RNS {2n − 1, 2
n , 2 n + 1}

MSR PROJECTS
Silent Features:
100% Pakka results
Documentation
Online support
PPT
Abstract
Extension
Base paper
Paper publishing(Min 3ip)
Plagiarism

2016 IEEE VLSI TITES FROM MSR PROJECTS-9581464142

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2016 IEEE VLSI TITES FROM MSR PROJECTS-9581464142