This document lists VLSI IEEE projects from 2016. It provides project codes and names for 24 projects related to areas like multipliers, floating point arithmetic, DSP acceleration, FIR filters, error correction codes, FFTs, modular arithmetic, and neuromorphic circuits. The document also provides contact information for Newzen Infotech, the organization hosting the projects. Most projects are listed as in the "Front End" stage, but a few related to analog/mixed-signal design and low-power circuits are in the "Back End" stage.

1. VLSI IEEE PROJECTS LIST
2016
2nd floor, Green Square Plaza, Opp: Geetha Bhavan, KARIMNAGAR-505 001.
Head Office: #201, 2nd Floor, Gyan Arcade, Ameerpet, HYDERABAD-500 082.
www.newzeninfotech.com , Ring on: +91 9030800005, +91 9052800005
PROJECT
CODE PROJECT NAME Design
VL1601
Pre-Encoded Multipliers Based on Non-Redundant Radix-4
Signed-Digit Encoding
Front End
VL1602
Floating-Point Butterfly Architecture Based on Binary Signed-
Digit Representation
Front End
VL1603
Flexible DSP Accelerator Architecture Exploiting Carry-Save
Arithmetic
Front End
VL1604
A High-Performance FIR Filter Architecture for Fixed and
Reconfigurable Applications
Front End
VL1605
A Method to Design Single Error Correction Codes
With Fast Decoding for a Subset of Critical Bits
Front End
VL1606 On Efficient Retiming of Fixed-Point Circuits Front End
VL1607 Concept, Design, and Implementation of Reconfigurable CORDIC Front End
VL1608
Fault Tolerant Parallel FFTs Using Error Correction Codes and
Parseval Checks
Front End
VL1609
Low-Power Parallel Chien Search Architecture Using a Two-Step
Approach
Front End
VL1610
An Efficient Single and Double-Adjacent Error Correcting Parallel
Decoder for the (24,12) Extended Golay Code
Front End
VL1611
Memory-Reduced Turbo Decoding Architecture
Using NII Metric Compression
Front End
VL1612
Multiple Constant Multiplication Algorithm for High-Speed and
Low-Power Design
Front End
VL1613 Design and Analysis of Inexact Floating-Point Adders Front End
VL1614
A Mixed-Decimation MDF Architecture for Radix-2k Parallel
FFT
Front End
VL1615
A Modified Partial Product Generator for Redundant Binary
Multipliers
Front End
VL1616
A Cellular Network Architecture With Polynomial Weight
Functions
Front End
VL1617
A Normal I/O Order Radix-2 FFT Architecture to Process Twin
Data Streams for MIMO
Front End
VL1618
High Speed Hybrid Double Multiplication Architectures Using
New Serial-Out Bit- Level Mastrovito Multipliers
Front End
VL1619
Low-Cost High-Performance VLSI Architecture for Montgomery
Modular Multiplication
Front End
VL1620
A High-Speed FPGA Implementation of an RSD-Based ECC
Processor
Front End
VL1621 VLSI Design for Convolutive Blind Source Separation Front End
VL1622
High-Speed and Energy-Efficient Carry Skip Adder Operating
Under a Wide Range of Supply Voltage Levels
Front End
VL1623
Input-Based Dynamic Reconfiguration of Approximate Arithmetic
Units for Video Encoding
Front End
VL1624
Hardware and Energy-Efficient Stochastic LU Decomposition
Scheme for MIMO Receivers
Front End

2. VLSI IEEE PROJECTS LIST
2016
2nd floor, Green Square Plaza, Opp: Geetha Bhavan, KARIMNAGAR-505 001.
Head Office: #201, 2nd Floor, Gyan Arcade, Ameerpet, HYDERABAD-500 082.
www.newzeninfotech.com , Ring on: +91 9030800005, +91 9052800005
VL1625 Hybrid LUT/Multiplexer FPGA Logic Architectures Front End
VL1626
High-Performance Pipelined Architecture of Elliptic Curve Scalar
Multiplication Over GF(2m)
Front End
VL1627
In-Field Test for Permanent Faults in FIFO Buffers of NOC
Routers
Front End
VL1628
Performance/Power Space Exploration for Binary64 Division
Units
Front End
VL1629 A High Throughput List Decoder Architecture for Polar Codes Front End
VL1630
A Novel Coding Scheme for Secure Communications in Distributed
RFID Systems
Front End
VL1631
Arithmetic algorithms for extended precision using floating point
expansions
Front End
VL1632
Digital Multiplierless Realization of Two-Coupled Biological
Hindmarsh–Rose Neuron Model
Front End
VL1633
A Low Power Trainable Neuromorphic Integrated Circuit That Is
Tolerant to Device Mismatch
Back End
VL1634
A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-
Power CMOS
Back End
VL1635
A Low-Power Incremental Delta–Sigma ADC for CMOS Image
Sensors
Back End
VL1636
Low-Power ASK Detector for Low Modulation Indexes and Rail-
to-Rail Input Range
Back End
VL1637
A Low-Power Robust Easily Cascaded PentaMTJ-Based
Combinational and Sequential Circuits
Back End
VL1638
PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique
for Low-Power Microprocessors
Back End
VL1639 Low-Power Variation-Tolerant Nonvolatile Lookup Table Design Back End
VL1640
Dual Use of Power Lines for Design-for-Testability—A CMOS
Receiver Design
Back End