This document contains a list of 111 VLSI projects with their titles and design status. The projects cover a wide range of topics related to VLSI design including multipliers, adders, SRAM cells, random number generators, encryption algorithms, and neural network accelerators. The design status is listed as either "Frontend" or "Backend" for each project.

2. VLSI PROJECTS LIST
S.NO PROJECT TITLE DESIGN
1. A Low-Power and High-Accuracy Approximate Multiplier With
Reconfigurable Truncation
Frontend
2. CRC-Based Correction of Multiple Errors Using an Optimized
Lookup Table
Frontend
3. Effective Hardware Accelerator for 2D DCT IDCT Using
Improved Loeffler Architecture
Frontend
4. Design of Approximate Radix-256 Booth Encoding for Error-
Tolerant Computing
Frontend
5. An Optimized M-Term Karatsuba-Like Binary Polynomial
Multiplier for Finite Field Arithmetic
Frontend
6. An Optimized M-Term Karatsuba-Like Binary Polynomial
Multiplier for Finite Field Arithmetic
Frontend
7. A Highly Secure FPGA-Based Dual-Hiding Asynchronous-
Logic AES Accelerator against Side-Channel Attacks
Frontend
8. FPGA Implementation of Reconfigurable CORDIC Algorithm
and a Memristive Chaotic System with Transcendental
Nonlinearities
Frontend
9. A Secure method for Image Signaturing using SHA 256, RSA,
and Advanced Encryption Standard (AES)
Frontend
10. TROT: A Three-Edge Ring Oscillator Based True Random
Number Generator with Time-to-Digital Conversion
Frontend
11. A High-Throughput VLSI Architecture Design of Canonical
Huffman Encoder
Frontend
12. A Novel Ultra-Compact FPGA-Compatible TRNG Architecture
Exploiting Latched Ring Oscillators
Frontend
13. A Low-Power and High-Accuracy Approximate Multiplier With
Reconfigurable Truncation
Frontend
14. A Low-Power and High-Accuracy Approximate Multiplier With
Reconfigurable Truncation
Frontend
15. Optimal Architecture of Floating-Point Arithmetic for Neural
Network Training Processors
Frontend
16. An Efficient and High-Speed Overlap-Free Karatsuba-Based
Finite-Field Multiplier for FGPA Implementation
Frontend

3. 17. Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm
with Key Schedule and Sub Bytes Block Optimization
Frontend
18. Transmission Gate -Based 8T SRAM Cell For Bio Medical
Applications
Frontend
19.
Low Power, High Performance PMOS Biased Sense Amplifier Backend
20. A High-Performance Core Micro-Architecture Based on RISC-
V ISA for Low Power Applications
Frontend
21. Constant-time Synchronous Binary Counter with Minimal
Clock Period
Frontend
22. Fast Binary Counters and Compressors Generated by Sorting
Network
Frontend
23. Design of Two Stage Operational Amplifier and Implementation
of Flash ADC
Frontend
24. A Very-Low-Voltage Frequency Divider in Folded MOS
Current Mode Logic With Complementary n- and p-type Flip-
Flops
Frontend
25. RandShift: An Energy-Efficient Fault-Tolerant Method in
Secure Nonvolatile Main Memory
Frontend
26. Two-Stage OTA with All Subthreshold MOSFETs and
Optimum GBW to DC-Current Ratio
Backend
27. A Three-Stage Amplifier with Cascode Miller Compensation
and Buffered Asymmetric Dual Path for Driving Large
Capacitive Loads
Backend
28. A Three-Stage Amplifier with Cascode Miller Compensation
and Buffered Asymmetric Dual Path for Driving Large
Capacitive Loads
Backend
29. A Reliable Low Standby Power 10T SRAM Cell with Expanded
Static Noise Margins
Backend
30. A High-Efficiency Fast-Transient LDO with Low-Impedance
Transient-Current Enhanced Buffer
Backend
31. A High CMRR Instrumentation Amplifier Employing Pseudo-
Differential Inverter for Neural Signal Sensing
Backend
32. Design of Three Stage Dynamic Comparator with Tail
Transistor using 20nm FinFET Technology for ADCs
Backend
33. High-Speed Area-Efficient VLSI Architecture of Three-
Operand Binary Adder
Frontend

4. 34. Data Retention based Low Leakage Power TCAM for Network
Packet Routing
Backend
35. A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in
55 nm MTCMOS
Backend
36.
Binary to gray code converter implementation using qca Front End
37. Design of a Reversible Floating-Point Square Root Using
Modified Non Restoring Algorithm
Front End
38. Design and Verification of DDR SDRAM Memory Controller
Using SystemVerilog For Higher Coverage
Front End
39. Concurrent Error Detectable Carry Select Adder with Easy
Testability
Front End
40.
The Mesochronous Dual-Clock FIFO Buffer Front End
41. A High-Performance Multiply-Accumulate Unit by Integrating
Additions and Accumulations into Partial Product Reduction
Process
Front End
42. Energy-Efficient Low-Latency Signed Multiplier for FPGA-
based Hardware Accelerators
Front End
43. An Efficient Parallel DA-Based Fixed-Width Design for
Approximate Inner-Product Computation
Front End
44.
Design of Power Efficient Posit Multiplier Front End
45. Design and analysis of High speed Wallace tree multiplier using
parallel prefix adders for VLSI circuit designs.
Front End
46.
Efficient Design for Fixed-Width Adder-Tree Front End
47. Hardware-Efficient Post-processing Architectures for True
Random Number Generators
Front End
48. Chaos-Based Bitwise Dynamical Pseudorandom Number
Generator on FPGA
Front End
49. Low-Power Approximate Unsigned Multipliers With
Configurable Error Recovery
Front End
50. Implementation of Ripple Carry and Carry Skip Adders with
Speed and Area Efficient
Front End
51.
Borrow Select Subtractor for Low Power and Area Efficiency Front End

5. 52. Rapid Balise Telegram Decoder with Modified LFSR
Architecture for Train Protection Systems
Front End
53. A Low-Power Yet High-Speed Configurable Adder for
Approximate Computing
Front End
54. High-Speed Area-Efficient VLSI Architecture of Three-
Operand Binary Adder
Front End
55. Design of 4:2 Compressor for Parallel Distributed Arithmetic
FIR Filter
Front End
56. PERFORMANCE ANALYSIS OF PARALLEL PREFIX
ADDER FOR DATAPATH VLSI DESIGN
Front End
57. Approximate Reverse Carry Propagate Adder for Energy-
Efficient DSP Applications
Front End
58. Architecture Optimization and Performance Comparison of
Nonce-Misuse-Resistant Authenticated Encryption Algorithms
Front End
59. TOSAM:AnEnergy-EfficientTruncation-andRounding-
BasedScalableApproximate Multiplier
Front End
60. Design And Analysis of Approximate Redundant Binary
Multipliers.
Front end
61. Rounding Technique Analysis Of Power-Area & Energy
Efficient Approximate Multiplier Design
Front end
62. A Combined Arithmetic-High-Level Synthesis Solution to
Deploy Partial Carry-Save Radix-8 Booth Multipliers in
Datapath.
Front end
63. Low Power High Accuracy Approximate Multiplier Using
Approximate High Order Compressors.
Front end
64. Efficient Modular Adder Designs Based on Thermometer &
One-Hot Encoding
Front End
65.
Error Detection And Correction In SRAM Emulated TCAMs Front end
66.
Efficient Design For Fixed Width Adder Tree Front end
67. Area –Time Efficient Streaming Architecture For Architecture
For FAST And BRIEF Detector
Front end
68. Hard Ware Efficient Post Processing Architecture For True
Random Number Generators
Front end
69.
A Two Speed Radix -4 Serial –Parallel Multiplier Front end

6. 70. Low power approximate unsigned multipliers with configurable
error recovery
Front end
71. Energy Quality Scalable Adders Based On Non Zeroing Bit
Truncation
Front end
72. Double MAC On A DSP Boosting The Performance Of
Convolutional Neural Networks On FPGAS
Front end
73. A Low-Power Parallel Architecture for Linear Feedback Shift
Registers
Front end
74. Ultra-low-voltage GDI-based hybrid full adder design for area and
energy-efficient computing systems
BACK
End
75. Design Of Area Efficient And Low Power 4-Bit Multiplier Based On
Full- swing GDI technique
BACK
End
76. Multistage Linear Feedback Shift Register Counters With Reduced
Decoding Logic in 130-nm CMOS for Large-Scale Array
Applications
BACK
End
77. Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced
Data-Independent Read Port Leakage for Array Augmentation in 32-
nm CMOS
BACK
End
78. Column selection enabled 10 T SRAM utilizing shared diff
VDD WRITE and dropped VDD read for FFT on real data.
BACK
End
79. Cell-state-distribution –assisted threshold voltage detector for
NAND flash memory
BACK
End
80. Efficient VLSI Implementation of a Sequential Finite Field
Multiplier Using Reordered Normal Basis in Domino Logic
BACK
End
81. An Approach to LUT Based Multiplier for Short Word Length
DSP Systems
Frontend
82. Novel High speed Vedic Multiplier proposal incorporating
Adder based on Quaternary Signed Digit number system
Frontend
83. FPGA Implementation of an Improved Watchdog Timer for
Safety-critical Applications
Frontend
84. Unbiased Rounding for HUB Floating-point Addition Frontend
85. A Low-Power Yet High-Speed Configurable Adder for
Approximate Computing
Frontend
86. A Low-Power High-Speed Accuracy-Controllable
Approximate Multiplier Design
Frontend
87. The Design and Implementation of Multi – Precision Floating
Point Arithmetic Unit Based on FPGA
Frontend

7. 88. Extending 3-bit Burst Error-Correction Codes With Quadruple
Adjacent Error Correction
Frontend
89. Efficient Modular Adders based on Reversible Circuits Frontend
90. MAES: Modified Advanced Encryption Standard for Resource
Constraint Environments
Frontend
91. Chip Design for Turbo Encoder Module for In-Vehicle System Frontend
92. Low-Power and Fast Full Adder by Exploring New XOR and
XNOR Gates
Backend
93. Low Power 4×4 Bit Multiplier Design using Dadda Algorithm
and Optimized Full Adder
Backend
94. Low Leakage Fully Half-Select-Free Robust SRAM Cells with
BTI Reliability Analysis
Backend
95. Improved 64-bit Radix-16 Booth Multiplier Based on Partial
Product Array Height Reduction
Frontend
96. Clock-Gating of Streaming Applications for Energy Efficient
Implementations on FPGAs
Frontend
97. An Improved DCM-Based Tunable True Random Number
Generator for Xilinx FPGA
Frontend
98. RoBA Multiplier: A Rounding-Based Approximate Multiplier
for High-Speed yet Energy-Efficient Digital Signal Processing
Frontend
99.
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA
Frontend
100.
Overloaded CDMA Crossbar for Network-On-Chip
Frontend
101.
Design of Power and Area Efficient Approximate Multipliers
Frontend
102. Scalable Approach for Power Droop Reduction During Scan-
Based Logic BIST
Frontend
103. Design of Low-Power High-Performance 2-4 and 4-16 Mixed-
Logic Line Decoders.
Backend
104. Performance Analysis of a Low-Power High-Speed Hybrid 1-bit
Full Adder Circuit
Backend

8. 105. 12T Memory Cell for Aerospace Applications in Nano scale
CMOS Technology
Backend
106. Pre-Encoded Multipliers Based on Non-Redundant Radix-4
Signed-Digit Encoding
Frontend
107. Flexible DSP Accelerator Architecture Exploiting Carry-Save
Arithmetic
Frontend
108. Low-Cost High-Performance VLSI Architecture for
Montgomery Modular Multiplication
Frontend
109. A High-Speed FPGA Implementation of an RSD-Based ECC
Processor
Frontend
110.
Hybrid LUT/Multiplexer FPGA Logic Architectures
Frontend
111. In-Field Test for Permanent Faults in FIFO Buffers of NOC
Routers
Frontend