Ieee 2020 21 vlsi projects in pondicherry,ieee vlsi projects in chennai

NEXGEN TECHNOLOGY
FINAL YEAR IEEE VLSI TITLES 2020-2021
CONTACT: PRAVEEN KUMAR. L (+91 – 9791938249)
MAIL ID: mailtonexgentech@gmail.com, Web:
www.nexgenproject.com,www.ijarcset.in
IEEE Transactions on VLSI 2020 Research Papers
LOW POWER
1. Vital-Sign Processing Receiver With Clutter Elimination Using Servo
Feedback Loop for UWB Pulse Radar System
2. RandShift: An Energy-Efficient Fault-Tolerant Method in Secure
Nonvolatile Main Memory

NEXGEN TECHNOLOGY
3. TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low
Supply Voltages
4. A Compact 0.3-V Class AB Bulk-Driven OTA
5. A Low-Power Reconfigurable Narrowband/Wideband LNA for Cognitive
Radio-Wireless Sensor Network
6. An Energy-Efficient Deep Convolutional Neural Network Inference
Processor with Enhanced Output Stationary Dataflow in 65-nm CMOS
7.
Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural
Networks
8. A Sub-1-V 100-mA OCL-LDO Regulator With Process-Temperature-Aware
Design for Transient Sustainability
9. A 600-mA, Fast-Transient Low-Dropout Regulator With Pseudo-ESR
Technique in 0.18- μ m CMOS Process
10.
A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme

NEXGEN TECHNOLOGY
11.Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write
Margin and Reliable Restore Yield
12.Gain-Cell Embedded DRAMs: Modeling and Design Space
13.MERIT: Tensor Transform for Memory-Efficient Vision Processing on
Parallel Architectures
14.A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly
Reflective Channels
15.A Low-Complexity Hybrid Readout Circuit for Lidar Receiver
16.A New High Drive Class-AB FVF-Based Second Generation Voltage
ConveYOR
17.Time-Domain Operational Amplifier With Voltage-Controlled Oscillator
and Its Application to Active-RC Analog Filter

NEXGEN TECHNOLOGY
18.A Low Phase Noise, High Phase Accuracy Quadrature LC-VCO With Dual-
Tail Current Biasing to Insert Reconfigurable Phase Delay
19. A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body
Bias Threshold Lowering
20.All-Digital Cost-Efficient CMOS Digital-to-Time Converter Using Binary-
Weighted Pulse Expansion
21.Radiation-Hardened 0.3–0.9-V Voltage-Scalable 14T SRAM and Peripheral
Circuit in 28-nm Technology for Space Applications
22.Optimizing FPGA Logic Circuitry for Variable Voltage Supplies
23. A High-Performance LDO Regulator Enabling Low-Power SoC With
Voltage Scaling Approaches
24.In-Memory Computing With Double Word Lines and Three Read Ports for
Four Operands

NEXGEN TECHNOLOGY
25.One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold
Operation
26.Power Efficient Tiny Yolo CNN Using Reduced Hardware Resources Based
on Booth Multiplier and WALLACE Tree Adders
27. High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–
XNOR Cell
28.Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast
Computation Balanced (3 + 2 log n)G Adders for Moduli Set {2n+1 , 2n +
2n−1 − 1, 2n+1 − 1}
AREA EFFICIENT/ TIMING & DELAY REDUCTION
1. The Mesochronous Dual-Clock FIFO Buffer
2. DART: A Framework for Determining Approximation Levels in an
Approximable Memory Hierarchy
3. Test Pattern Generation and Critical Path Selection in the Presence of
Statistical Delays
4. Low-Complexity Distributed-Arithmetic-Based Pipelined Architecture for
an LSTM Network

NEXGEN TECHNOLOGY
5. Algorithm and Architecture of an Efficient MIMO Detector With Cross-
Level Parallel Tree-Search
6. Conflux—An Asynchronous Two-to-One Multiplexor for Time-Division
Multiplexing and Clockless, Tokenless Readout
7. Slicing FIFOs for on-chip memory bandwidth exhaustion
8. Res-DNN: A Residue Number System-Based DNN Accelerator Unit
9. Design Method for Online Totally Self-Checking Comparators
Implementable on FPGAs
10.Automated Design of Reconfigurable Microarchitectures for Accelerators
Under Wide-Voltage Scaling
11.POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator
12.N -Dimensional Approximation of Euclidean Distance
13.A Stochastic Computing Architecture for Iterative Estimation

NEXGEN TECHNOLOGY
14.FPGA-Based True Random Number Generation Using Programmable
Delays in Oscillator-Rings
15.Runtime Efficiency-Accuracy Tradeoff Using Configurable Floating Point
Multiplier
16. ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-
Addressable Memory for FPGAs
17.Optimal Runtime Algorithm to Improve Fault Tolerance of Bus-Based
Reconfigurable Designs
18. GH CORDIC-Based Architecture for Computing N th Root of Single-
Precision Floating-Point Number
19.Design Exploration of Energy-Efficient Accuracy-Configurable Dadda
Multipliers With Improved Lifetime Based on Voltage Overscaling
20.An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-
Product Computation
21.Design of Approximate Booth Squarer for Error-Tolerant Computing

NEXGEN TECHNOLOGY
22.Parallel architecture of power-of-two multipliers for FPGAs
23.
Low-Latency Reconfigurable Entropy Digital True Random Number
Generator With Bias Detection and Correction
24.Stochastic Mixed-PR: A Stochastically-Tunable Low-Error Adder
25.Area–delay and energy efficient multi-operand binary tree adder
26.Block-Based Carry Speculative Approximate Adder for Energy-Efficient
Applications
27.Optimizing FPGA Logic Block Architectures for Arithmetic
28.RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable
Memory on FPGAs
29.Fast Hybrid Karatsuba Multiplier for Type II Pentanomials

NEXGEN TECHNOLOGY
30.Design Approach for Ring Amplifiers
31.Comparison and Extension of Approximate 4-2 Compressors for Low-
Power Approximate Multipliers
32.Design and Implementation of a Low-Latency Modular Multiplication
Algorithm
HIGH SPEED DATA TRANSMISSION
1. A Highly Efficient Conditional Feedthrough Pulsed Flip-Flop for High-
Speed Applications
2. ASP-SIFT: Using Analog Signal Processing Architecture to Accelerate
Keypoint Detection of SIFT Algorithm
3. An FPGA-Based 1-GHz, 128 × 128 Cross-Correlator for Aperture Synthesis
Imaging
4. AddNet: Deep Neural Networks Using FPGA-Optimized MultipliersA
Novel Time-Shared and LUT-Less Pipelined Architecture for LMS
Adaptive Filter

NEXGEN TECHNOLOGY
5. A 10-Gb/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations
in 65-nm CMOS
6. A 2.56-Gb/s Serial Wireline Transceiver That Supports an Auxiliary
Channel in 65-nm CMOS
7. Design and Implementation of Encryption/Decryption Architectures for
BFV Homomorphic Encryption Scheme
8. High-Resolution All-Digital Transmit Beamformer for High-Frequency and
Wearable Ultrasound Imaging Systems
9. A Compact Fully Passive Loop Filter-Based Continuous Time Modulator
for Multi-Channel Biomedical Applications
10. Incremental Fault Analysis: Relaxing the Fault Model of Differential Fault
Attacks
11.Jitter Minimization in Digital PLLs with Mid-Rise TDCs
12.A Scan Obfuscation Guided Design-for-Security Approach for Sequential
Circuits
13.RLWE-Oriented High-Speed Polynomial Multiplier Utilizing Multi-Lane
Stockham NTT Algorithm
14. DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-
Error-Rate Reduction

NEXGEN TECHNOLOGY
15. Approximate memory compression for energy-efficiency
16. A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With
Time-Based Feedforward Equalization in a 28-nm CMOS
17.A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-
Tap Decision-Feedback Equalizer in 28-nm CMOS
18. Analysis and Design of Unified Architectures for Zero-Attraction-Based
Sparse Adaptive Filters
19. High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary
Adder
20.High Throughput Spatial Convolution Filters on FPGAs
21.A 0.6-V Power-Efficient Active-RC Analog Low-Pass Filter With Cutoff
Frequency Selection
22.An Analytical Jitter Tolerance Model for DLL-Based Clock and Data
Recovery Circuits
AUDIO / IMAGE & VIDEO Processing
1. A Low-Cost and High-Throughput FPGA Implementation of the Retinex
Algorithm for Real-Time Video Enhancement

NEXGEN TECHNOLOGY
2. A Modified Inexact Arithmetic Median Filter for Removing Salt-and-Pepper
Noise From Gray-Level Images
3. FPGA-Based Implementation of a Real-Time Object Recognition System
Using Convolutional Neural Network

Ieee 2020 21 vlsi projects in pondicherry,ieee vlsi projects in chennai

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