1. The document describes the design and implementation of a mod 6 direct down counter using J-K flip flops and the synchronous counters method. 2. The design exploits Karnaugh maps to determine the logic inputs for each J-K flip flop in order to minimize the logic functions. 3. The mod 6 down counter is implemented using Electronic Workbench software with 3 J-K flip flops that count synchronously from 5 to 0 on each clock pulse before repeating the cycle.

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International Journal of Electronics and Communication Engineering & Technology
(IJECET)
Volume 6, Issue 7, Jul 2015, pp. 31-36, Article ID: IJECET_06_07_005
Available online at
http://www.iaeme.com/IJECETissues.asp?JTypeIJECET&VType=6&IType=7
ISSN Print: 0976-6464 and ISSN Online: 0976-6472
© IAEME Publication
___________________________________________________________________________
EXPLOITING DESIGN OF SYNCHRONOUS
COUNTERS METHOD TO DESIGN AND
IMPLEMENT MOD 6 DIRECT DOWN
COUNTER
Bawar A. Abdalla and Zhenar Sh. Faeq
Department of Software Engineering, Faculty of Engineering,
University of Koya, Koya, Iraq
Zrar Kh. Abdul
Department of General Science, University of Charmo, Chamchamal, Iraq
ABSTRACT
In this paper, the design of direct mod 6 down counter is proposed by
using J-K Flip Flop. The counter is provided with synchronous clock pulse.
The counter is implemented by using Electronic Workbench software. The
design can be achieved by the logical function minimization using Karnaugh
map. Vcc and Ground are used for inputs to indicate logic 1 and 0
respectively as well as LED indicators are used to indicate the output bits. The
proposed design is practical to implement any modulus of direct down
counters which can count from any number to zero. This can have advantage
over partial decoding method to design counters which their modulus does not
belong to 2n
sequence because partial decoding method is only practical for
up counters.
Key words: Down Counter, Mod 6 Down Counter and Synchronous
Counters.
Cite this Article: Abdalla, B. A., Faeq, Z. S. and Abdul, Z. K. Exploiting
Design of Synchronous Counters Method to Design and Implement Mod 6
Direct Down Counter. International Journal of Electronics and
Communication Engineering & Technology, 6(7), 2015, pp. 31-36.
http://www.iaeme.com/IJECET/issues.asp?JTypeIJECET&VType=6&IType=7
_____________________________________________________________________
1. INTRODUCTION
Counting is a fundamental function of digital circuits [1]. It can be performed by
counters which are named as sequential circuits that change their states by the clock

2. Bawar A. Abdalla, Zhenar Sh. Faeq and Zrar Kh. Abdul
http://www.iaeme.com/IJECET/index.asp 32 editor@iaeme.com
pulses applied on their inputs. They can be used in real world applications ranging
from a simple display to complex microcontroller circuits. Some of the applications
are digital systems, with applications in computer systems, communication
equipment, scientific instruments, and industrial control [2]. Obviously, the counters’
primary function is producing a sequence of different output patterns. Hence, they
also can be named as pattern generators. These sequence of pattern scan be assigned
to a number of an event’s occurrences as well as it can be used to control and select
each specific part of a digital system. In this way each output state of pattern indicates
the performance of each distinct part of the digital system [3]. Basically, a counter is a
logic circuit that counts up to a specific number. Each count is a binary number as
well as called the state of the counter. Moreover, the number of states of a counter is
called modulus of the counter and can be determined by the number of bits used to
design the counter. Thus, an n bit counter has 2n
states and called as module 2n
counter where n is an integer number [2].
It is clear that essential elements that associated in designing the semiconductor
devices are Flip Flops [4]. There are many types of Flip Flops such as SR, D, T and
JK. They can be connected together to perform the function of a counter. This means
a group of Flip Flops is a counter, the number of states and the modulus of the counter
can be determined through the number of Flip Flops whereas each Flip Flop holds one
binary bit in the output pattern of the counter. In addition, according to the connection
design of the Flip Flops together and the way the counter circuits are clocked, the
Counters can be categorized in to two main categories which are asynchronous and
synchronous. In asynchronous counters each Flip Flop receives clock pulse from the
previous Flip Flop while in the synchronous counters all the Flip Flops are receiving
their clock pulses simultaneously [5].
2. BACKGROUND
2.1 J-K Flip-Flop
J-K Flip-flop is like the other Flip Flops while the outputs are affected by the inputs
when the Clock is high for positive edges and low for negative edges, also there are
two inputs associated with this type of Flip Flop which are labeled as J and K.
Furthermore, if both J and K are low and the clock pulse is applied, the output will not
change as it stays as the same as the previous output state. If both J and K are high,
the output will toggle from the previous output state. Finally, if J and K are different
and the clock is applied the output state will follow the J input [10, 11]. The
advantage of J-K Flip Flop is that it does not have any invalid state as occurred in S-R
Flip Flop while both S and R are high [8]. Table 1 shows the truth table of J-K Flip
Flop.
Table 1 J-K Flip Flop Truth table
Moreover, the J-K Flip Flop Transition table can be seen from Table 2.

3. Exploiting Design of Synchronous Counters Method to Design and Implement Mod 6 Direct
Down Counter
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Table 2 J-K Flip Flop Transition table
2.2. Counter Modulus
Counters can perform up counting to a maximum state according to the number of
Flip Flops. For example, 2 bits counter has 22
states which can count from zero to
three. This is called up counter. However, down counter produces a sequence from the
maximum state to zero. For example, 3 bits counter can produce a sequence from
seven to zero. In some applications, it is required that the counter should perform both
up and down counting which is called up/down counter [6]. According to number of
Flip Flops in the counters, the modulus of the counters is 2,4,8,16,32 and etc. This is
because of that the number of states is 2n
where n is the number of Flip Flops.
However, some applications might need a modulus which is not in the 2n
sequence
such as modulus 4, 6, 7 and 9. In this case, there should be a mechanism to reset the
counter after the maximum required state such as modulus 6 counts from 0 to 5 and
should be cleared at the state of 6. This mechanism is called partial decoding [5]. In
addition, this mechanism is only practical for up counters while it doesn’t work for
down counters. The aim of this paper is to exploit synchronous counter design to
implement a practical high performance synchronous down counter which its modulus
doesn’t belong to the 2n
sequences such as modulus 6 down counter as a case study by
using Electronic Workbench Software.
In this paper, Electronics Workbench (EWB) has been used to design and simulate
the circuit since it is friendly as well as it provides an interface as close as to the real
implementation environment [7]. It provides TTL logic levels (+Vcc) used to indicate
logic high for the inputs. It also provides an output circuit which is called “indicator
lamp” to represent the output state of a single bit, it indicates logic high in case when
it turns on, and else it indicates logic 0 [9].
3. DESIGNING AND TESTING THE MOD 6 DOWN COUNTER
To start with, synchronous counters need some special mathematical calculations.
This can be done by drawing the counter state diagram as can be seen from Figure 1.
Figure 1 Counter state diagram
After that, the table of the counter’s logical function can be built as it is shown in
table (3). This can be done by listing each present state of the counter with the
corresponding next state [5].
Q N Q N+1 J K
0 0 0 X
0 1 1 X
1 1 X 0
1 0 X 1

4. Bawar A. Abdalla, Zhenar Sh. Faeq and Zrar Kh. Abdul
http://www.iaeme.com/IJECET/index.asp 34 editor@iaeme.com
Table 3 Counter’s logical function.
Then, Karnaugh map can be used to calculate and determine the logic input of
each J and K of each Flip Flop as shown in Figure 2.
Figure 2 Karnaugh Map Minimization of each J and K of each Flip Flop
Finally, the proposed counter can be designed by using the logic functions found
through the Karnaugh Maps by using Electronic Work Bench Software as shown in
Figure 3.

5. Exploiting Design of Synchronous Counters Method to Design and Implement Mod 6 Direct
Down Counter
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Figure 3 The Mod 6 Down Counter.
As can be seen from the above figure the modulus 6 down counter was designed
using 3 flip flops where the flip flop corresponding to Q0 is Least Significant Bit while
the one corresponding to Q2 is Most Significant Bit. Flip Flops are clocked
synchronously with negative transition of the input clock pulse (C). It is clear that the
three output indicators are initially off because the counter is initially is in 0 state
which is 000 in binary. However, when a negative transition of the C input is applied
synchronously, the counter output will change to 5 which is 101 in binary. This can be
seen in Figure 4.
Figure 4 The Mod 6 Down counter while output is 5.
If another clock pulse is applied to the counter. It will change its state to 4.
Moreover, with each negative transition of the input clock pulse the counter decrease
by 1 until it reaches 0. Then, it will repeat its sequence from 5 to 0 again. The above
method can be exploited to design those down counters which there modulus do not
follow 2n
sequences.

6. Bawar A. Abdalla, Zhenar Sh. Faeq and Zrar Kh. Abdul
http://www.iaeme.com/IJECET/index.asp 36 editor@iaeme.com
4. CONCLUSION
In conclusion, J-K Flip Flops were used to design the synchronous mod 6 down
counter. The input of each J and K of the Flip Flops can be determined through the
counter’s logical function and Karnaugh map. The proposed counter was designed
and implemented by using electronic workbench software which is sufficient for
designing purposes. The counter could count from 5 to 0 by applying synchronous
clock pulses to the negative edges of each Flip Flop. It can be suggested that the
exploited method to design the counter is practical to design any modulus of direct
down counters as well as for up counters.
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