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unit 1.pptx

A microprocessor is a computer processor where the data processing logic and control is included on a single integrated circuit (IC), or a small number of ICs.

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By – R. R. BORNARE
Sanjivani K. B. P. Polytechnic College, Kopargaon
8086 Microprocessor
 16-bit microprocessor.
 It can transfer 16-bit address and operates on 16-bit
data at a time.
 Every activity that 8086 does, it is capable of
working on 16-bits of information in one operation or
one cycle.
 The architecture is basically divided into 2 units;
- BIU (Bus Interface Unit)
- EU (Execution Unit)
Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
Why is the architecture divided
into 2 Units?
Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
The reason is Pipelining...
 Before, a process use to fetch one instruction, then
execute that instruction (8085 up).
ie. Working on only one instruction..F1E1F2E2..
 In 8086, while we fetch one instruction and starts its
execution, it will side by side fetch the next instruction.
ie. Working on next instruction..F1E1E2E3..
Fetching is done simultaneously.
 So, in 8086 architecture, while BIU unit is fetching one
instruction, after fetching it will send the instruction to
the execution unit. Meanwhile, BIU will fetch next
instruction.
Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
Note
 Remember, no matter how complex an
architecture looks, at the end it is a processor.
 So, just trace the path. ie.
- How is an instruction is fetched, then
- Where it is decoded and
- Finally where it gets executed.
 If you are able to trace the path, you can learn
any type of complex microprocessor architecture
possible.
Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
8086 Architecture
Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare

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unit 1.pptx

  • 1. By – R. R. BORNARE Sanjivani K. B. P. Polytechnic College, Kopargaon
  • 2. 8086 Microprocessor  16-bit microprocessor.  It can transfer 16-bit address and operates on 16-bit data at a time.  Every activity that 8086 does, it is capable of working on 16-bits of information in one operation or one cycle.  The architecture is basically divided into 2 units; - BIU (Bus Interface Unit) - EU (Execution Unit) Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
  • 3. Why is the architecture divided into 2 Units? Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
  • 4. The reason is Pipelining...  Before, a process use to fetch one instruction, then execute that instruction (8085 up). ie. Working on only one instruction..F1E1F2E2..  In 8086, while we fetch one instruction and starts its execution, it will side by side fetch the next instruction. ie. Working on next instruction..F1E1E2E3.. Fetching is done simultaneously.  So, in 8086 architecture, while BIU unit is fetching one instruction, after fetching it will send the instruction to the execution unit. Meanwhile, BIU will fetch next instruction. Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
  • 5. Note  Remember, no matter how complex an architecture looks, at the end it is a processor.  So, just trace the path. ie. - How is an instruction is fetched, then - Where it is decoded and - Finally where it gets executed.  If you are able to trace the path, you can learn any type of complex microprocessor architecture possible. Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
  • 6. 8086 Architecture Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
  • 7. Concentrate on BIU.. Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
  • 8. BIU Unit 1. It provides the interface of 8086 to other devices. 2. It operates w.r.t. Bus cycles . - This means it performs various machine cycles such as Memory Read, IO Write etc to transfer data with Memory and I/O devices. 3. It performs the following functions: a) It generates the 20-bit physical address for memory access. b) Fetches Instruction from memory. c) Transfers data to and from the memory and IO. d) Supports Pipelining using the 6-byte instruction queue. Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
  • 9. The main components of the BIU are:  Segment Registers  Instruction Pointer  Address Generation Circuit  6-Byte Pre-Fetch Queue Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
  • 10. Considering all the shapes in the architecture...  Everything in the architecture is in the shape of rectangle..  Besides, the ALU and   So, whenever we see this shape, remember it is a symbol of arithmetic circuit, ie. some arithmetic operation is taking place inside it.. Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
  • 11. Consider, ALU... It is a 16-bit ALU. It performs 8 and 16-bit arithmetic and logic operations. Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
  • 12. Consider,   Example: ADD BL,CL  Here, we have two registers in above example. So, What will be the purpose of  Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
  • 13. Continued..  This symbol is used to calculate the Physical Address.  ie. PA = Seg addr * 10H + offset addr.  “Whenever, the ALU is busy in executing an instruction, the BIU will fetch the next instruction by calculating its Physical Address”. Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
  • 14. Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
  • 15. Address Generation Circuit  The BIU has a Physical Address Generation Circuit. It generates the 20- bit physical address using Segment and Offset addresses using the formula:  Physical address = Segment Address x 10h + Offset Address  Viva Question: Explain the real procedure to obtain the Physical Address? - The Segment address is left shifted by 4 positions, this multiplies the number by 16 (i.e. 10h) and then the offset address is added.  Eg: If Segment address is 1234h and 0ffset address is 0005h, then the physical address (12345h) is calculated as follows: i. 1234h = (0001 0010 0011 0100)binary Left shift by four positions and we get (0001 0010 0011 0100 0000)binary i.e. 12340h ii. Now add (0000 0000 0000 0101)binary i.e. 0005h and we get (0001 0010 0011 0100 0101)binary i.e. 12345h. Sanjivani K. B. P.Polytechnic College,Kopargaon Prof: R.R.Bornare
  • 16. What is the purpose of this block? Are these segments or registers? Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 17. Continued..  These are all 16-bit segment registers.  They contain address of all the segments.  CS tells where the code segment begins in memory.  SS gives the starting address of stack segment and so on..  Similarly, the IP will give the offset address of the segment. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 18. Explanation  So, whenever the next instruction is fetched from the memory, by the processor, every time IP will be incremented and will point to the address of next instruction.  All the segment address and IP(offset addr) are combined to calculate the PA. This will give us the location of next instruction which is to be fetched through the address bus.  Then, from the memory, the instruction is fetched inside the processor through the databus. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 19. Segment Registers 1. CS Register:  CS holds the base (Segment) address for the Code Segment.  All programs are stored in the Code Segment.  It is multiplied by 10H (16d), to give the 20-bit physical address of the Code Segment.  Eg: If CS = 4321H then CS × 10H = 43210H→Starting address of Code Segment.  CS register cannot be modified by executing any instruction except branch instructions. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 20. 2. DS Register:  DS holds the base (Segment) address for the Data Segment.  It is multiplied by 10H (16d), to give the 20-bit physical address of the Data Segment.  Eg: If DS = 4321H then DS × 10H = 43210H → Starting address of Data Segment. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 21. 3. SS Register:  SS holds the base (Segment) address for the Stack Segment.  It is multiplied by 10H (16d), to give the 20-bit physical address of the Stack Segment.  Eg: If SS = 4321H then SS × 10H = 43210H → Starting address of Stack Segment. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 22. 4. ES Register  ES holds the base (Segment) address for the Extra Segment.  It is multiplied by 10H (16d), to give the 20-bit physical address of the Extra Segment.  Eg: If ES = 4321H then ES × 10H = 43210H → Starting address of Extra Segment. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 23. Instruction Pointer(IP register)  It is a 16-bit register.  It holds offset of the next instruction in the Code Segment.  Address of the next instruction is calculated as CS x 10H + IP.  IP is incremented after every instruction byte is fetched.  IP gets a new value whenever a branch occurs. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 24. 6-Byte Prefetch Queue  We are fetching the next instruction in advance. This process is called as Prefetching.  These instructions fetched in advance arestored in a 6-Byte Prefetch Queue. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 25. Continued..  All the future instructions will come in the queue.  When queue wants to execute the instructions then, it will go on removing the instructionsone by one from the queue.  As queue removes more instructions, BIU fetches instructions and move them in thequeue. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 26. Bytes & Instructions are not same..  Instructions can be of the size; 1 byte, 2 byte, 3 byte and so on..  Our queue is of 6-bytes so, it can hold the biggest possible instruction of 6-bytes.  Suppose, instructions are of different sizes.. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 27.  This queue is of 6-byte. What does that mean?  That means, we have 6-bytes of a program in our queue.  We don’t know the number of instructions, we only know the number of bytes. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 28. Examples MOV BL, CL; (register value of CL comes in BL) MOV BL, 25H; (register BL gets value 25) MOV BX, 2000H; (BX register gets value 2000H)  Every instruction has its uniqueopcode.  When assembly language is converted into machine language, it will get anopcode. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 29. Consider Instructions..  MOV BL, CL; (Opcode for the whole instruction)  MOV BL, 25H; (?) Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 30. Note..  No, it will have an opcode only for MOVBL (assembly language).  It will not have code for 25H(operand).  Reason: “If we have opcode for 25H..,then we should have an opcode for 26H,27H,.....so on.(ie. infinite opcodes. So, a number is never included in opcode”.  Opcode specify operations.  Opcode specify registers. Because, both are limited. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 31. Why are we using Queue not Stack?  As we know, that different instructions are of different sizes.  While we are executing an instruction, the next bytes of the program are taken and stored into the 6-bytes queue called object.  Then why Queue? Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 32. Reason “Because the order in which the instructions are fetched, should be same in which they will be executed.” Using stack will give you the reverse order of instructions. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 33. When will the BIU refill the Queue?  When the ALU wants to execute the next instruction, every time the queue will go on emptying..  So, after sometime or the other, BIU will always need to refill the queue.  But, when will the BIU refill the queue?  If we decide to refill the queue, when the whole queue is emptied, the ALU will have to wait for long time. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 34. Note.. The BIU transferring will refill the queue 2-bytes (16-bits) of after data. Because we have 16-bit processor. As, it can transfer 2-bytes in one cycle. So, why waste 2-cycles...  Now, if the forth coming instruction is of 4- bytes then whether the queue will fetch it or not? Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 35. Answer  Yes, it will fetch and store half bytes of the instruction.  Because till its time of comes, the queue will become full, as the biggest instruction fetched is of 6-bytes from the queue. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 36. 6-Byte Pre-Fetch Queue  It is a 6-byte FIFO RAM used to implement Pipelining.  Fetching the next instruction while executing the current instruction is called Pipelining.  BIU fetches the next “six instruction-bytes” from the Code Segment and stores it into the queue.  Execution Unit (EU) removes instructions from the queue and executes them.  The queue is refilled when atleast two bytes are empty as 8086 has a 16-bit data bus.  Pipelining increases the efficiency of the μP.  Pipelining fails when a branch occurs, as the pre-fetched instructions are no longer useful.  Hence as soon as 8086 detects a branch operation, it clears/discards the entire queue. Now, the next six bytes from the new location (branch address) are fetched and stored in the queue and Pipelining continues. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 37. Control Section  Control section is used to decode theinstructions. All the instructions transferred from the queuewill be decoded in the control section. After decoding control section will releasethe control signals (RD, WR) all over theprocessor.  Control unit will tell the ALU what operationneeds to be performed. (Opcode of any operation will come here) The operands will come here (eg: 04H, 05H) Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 38. Consider Execution Unit One track purpose, to execute the instructions. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 39. Execution Unit 1. It fetches instructions from the Queue in BIU, decodes and executes them. 2. It performs arithmetic, logic and internal data transfer operations. 3. It sends request signals to the BIU to access the external module. 4. It operates w.r.t. T-States (clock cycles). Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 40. The main components of the EU are:  General Purpose Registers  Special Purpose Registers  ALU  Operand Register  Instruction Register and Instruction Decoder  Flag Register Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 41. Registers (16-bits) Given to the programmers. They have special purpose to give the offset address. (Higher bytes) (Lower bytes) AX BX CX DX (16-bits) Consider number 1234; so using two 8-bits registers; we can store the number as, 12 34 AH AL Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 42. General Purpose Registers 8086 has four 16-bit general-purpose registers AX, BX, CX and DX. These are available to the programmer, for storing values during programs. Each of these can be divided into two 8-bit registers such as AH, AL; BH, BL; etc. Beside their general use, these registers also have some specific functions. 1. AX Register (16-Bits)  It holds operands and results during multiplication and division operations.  All IO data transfers using IN and OUT instructions use A register (AL/AH or AX).  It functions as accumulator during string operations. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 43. 2. BX Register (16-Bits)  Holds the memory address (offset address), in Indirect Addressing modes. 3. CX Register (16-Bits)  Holds count for instructions like: Loop, Rotate, Shift and String Operations. 4. DX Register (16-Bits)  It is used with AX to hold 32 bit values during Multiplication and Division.  It is used to hold the address of the IO Port in indirect IO addressing mode. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 44. Special Purpose Registers 1. Stack Pointer (SP 16-Bits)  It is holds offset address of the top of the Stack. Stack is a set of memory locations operating in LIFO manner. Stack is present in the memory in Stack Segment.  SP is used with the SS Register to calculate physical address for the Stack Segment. It used during instructions like PUSH, POP, CALL, RET etc. During PUSH instruction, SP is decremented by 2 and during POP it is incremented by 2. 2. Base Pointer (BP 16-Bits)  BP can hold offset address of any location in the stack segment.  It is used to access random locations of the stack. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 45. 3. Source Index (SI 16-Bits)  It is normally used to hold the offset address for Data segment but can also be used for other segments using Segment Overriding. It holds offset address of source data in Data Segment, during String Operations. 4. Destination Index (DI 16-Bits)  It is normally used to hold the offset address for Extra segment but can also be used for other segments using Segment Overriding. It holds offset address of destination in Extra Segment, during String Operations. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 46. Consider Examples..  MOV CL, 34H;  MOV CH, 12H;  MOV CX, 1234H; (CL=34) (CH=12) (CH=12, CL=34)  MOV BL, CL; (BL CL) ↑ ↑(Value of CL gets duplicated/copied in BL) (Destination) (Source)  MOV BH, CH;  MOV BX, CX; (BH  CH) (for 16- bits) Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 47. Program to add two numbers  04H + 05H = 09H ↓ ↓ BL CL ↓ BL  MOV BL, 04H  MOV CL, 05H  ADD BL, CL; (BL  BL+CL) Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 48. Using only one register BL..  MOV BL, 04H  ADD BL, 05H Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 49. Instruction Register & Instruction Decoder  It is present inside the Control Unit.  The EU fetches an opcode from thequeue into the Instruction Register.  The Instruction Decoder decodes it and sends the information to the control circuit for execution. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 50. Temporary Registers  Consider Example;  XCHG BX, CX; (For storing the value of CX in BX. First we need to store the value of BX, to not lose the value it contains.)  To store such values we have Operands.  They are only available to the processor, for storing temporary values. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 51. Operand Register  It is a 16-bit register used by the control register to hold the operands temporarily.  It is not available to the Programmer. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 52. Flag Registers  It contains various flags.  Each flag will give status about the current result. Sanjivani K. B. P.Polytechnic College,Kopargaon
  • 53. THANK YOU Sanjivani K. B. P.Polytechnic College,Kopargaon