The document discusses the SIC/SIC-XE machine architecture and assemblers. It provides details on the hardware units, registers, memory, instruction formats, addressing modes, instruction sets, and I/O of SIC/SIC-XE machines. It also discusses system software, differences between system and application software, and provides examples of code in SIC and SIC/XE languages. Finally, it covers the functions of an assembler, the different records used in the object file format, and the key data structures used in assembler design including the operation code table, symbol table, and location counter.
Assembler is a kind of system software that translate mnemonic codes written in assembly language (which is, in turn, a low-level language) into its equivalent object code (which is, in turn, need to change into executable code by loader and linker)
A single pass assembler scans the program only once and creates the equivalent binary program. The assembler substitute all of the symbolic instruction with machine code in one pass.
Assembler is a kind of system software that translate mnemonic codes written in assembly language (which is, in turn, a low-level language) into its equivalent object code (which is, in turn, need to change into executable code by loader and linker)
A single pass assembler scans the program only once and creates the equivalent binary program. The assembler substitute all of the symbolic instruction with machine code in one pass.
This slide contain the description about the various technique related to parallel Processing(vector Processing and array processor), Arithmetic pipeline, Instruction Pipeline, SIMD processor, Attached array processor
Lex is officially known as a "Lexical Analyser".
Yacc (for "yet another compiler compiler." ) is the standard parser generator for the Unix operating system.
Register Reference Instructions are those instructions that refer the registers to retrieve data from or to deposit data at. Copy the link given below and paste it in new browser window to get more information on Register Reference Instructions:- http://www.transtutors.com/homework-help/computer-science/computer-architecture/register-reference-instructions/
Assemblers Elements of Assembly Language Programming, Design of the Assembler, Assembler Design Criteria, Types of Assemblers, Two-Pass Assemblers, One-Pass Assemblers, Single pass Assembler for Intel x86 , Algorithm of Single Pass Assembler, Multi-Pass Assemblers, Advanced Assembly Process, Variants of Assemblers Design of two pass assembler
Compiler Construction
Phases of a compiler
Analysis and synthesis phases
-------------------
-> Compilation Issues
-> Phases of compilation
-> Structure of compiler
-> Code Analysis
This slide contain the description about the various technique related to parallel Processing(vector Processing and array processor), Arithmetic pipeline, Instruction Pipeline, SIMD processor, Attached array processor
Lex is officially known as a "Lexical Analyser".
Yacc (for "yet another compiler compiler." ) is the standard parser generator for the Unix operating system.
Register Reference Instructions are those instructions that refer the registers to retrieve data from or to deposit data at. Copy the link given below and paste it in new browser window to get more information on Register Reference Instructions:- http://www.transtutors.com/homework-help/computer-science/computer-architecture/register-reference-instructions/
Assemblers Elements of Assembly Language Programming, Design of the Assembler, Assembler Design Criteria, Types of Assemblers, Two-Pass Assemblers, One-Pass Assemblers, Single pass Assembler for Intel x86 , Algorithm of Single Pass Assembler, Multi-Pass Assemblers, Advanced Assembly Process, Variants of Assemblers Design of two pass assembler
Compiler Construction
Phases of a compiler
Analysis and synthesis phases
-------------------
-> Compilation Issues
-> Phases of compilation
-> Structure of compiler
-> Code Analysis
8 bit Microprocessor with Single Vectored InterruptHardik Manocha
SoC consists of instruction memory, main memory and microprocessor unit. Instructions are fetched using PC and as per the instruction, main memory and register memory are accessed. 8 bit data bus is built. Working on developing programs to look for microprocessor operation.
4bit pc report[cse 08-section-b2_group-02]shibbirtanvin
Report on Very Simple Computer Design & Implementation_
4bit PC_DSD_report[CSE-08_Section-B2_Group-02]
Courtesy:
Tanvir Al Amin Popel
Tanvir Ahmed Khan
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Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
Forklift Classes Overview by Intella PartsIntella Parts
Discover the different forklift classes and their specific applications. Learn how to choose the right forklift for your needs to ensure safety, efficiency, and compliance in your operations.
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NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
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Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
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Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
3. Chapter 1: SIC/SIC-XE Machine
Architecture
Hardware units
Input Devices
Output Devices
Hardware System Unit Ex: CPU, Memory,
N/W Card, Power Supply, Graphics
Card Etc
Storage Devices
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
4. System Software
System Software is a set of programs that support the
operation of a computer.
It consist of a variety of programs that support the
operations of a computer.
The system software manages the computer resources
while processing the data and control various
hardware components
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
5. Difference Between System
Software And Application Software
SYSTEM SOFTWARE APPLICATION SOFTWARE
1 System software is machine
dependent
Application software is machine
independent
2 Focus is on the operation that with
computer as a took rather than
application
Focus is on the application not on the
computing system
3 It is middleware that runs the
infrastructure that supports the
application software
Application software that most of the
end users are familiar with and where
the work is done by average persons
4 Development of system software is
complex
Development of application software
is easier when compared to system
software
5 Ex: assemblers translate mnemonic
instructions into machine code
instruction formats etc
Ex: word processors, spreadsheets,
media players etc
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
6. SIC [Simplified Instruction Computer]
Design to list the most commonly encountered habit
features and the concepts of while avoiding most of the
idiosyncrasies often that are found in real machines
The SIC architecture depends upon on the following
features:
1. Memory
2. Register
3. Data Formats
4. Instruction Formats
5. Addressing Modes
6. Instruction Set
7. Input and output
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
7. 1. MEMORY
The number of address lines in standard model of SIC
is 15.
So , the size of the memory that can be addressed = 215
=32768 bytes.
Memory consists of 8 bits that makes one byte
Any three consecutive bytes form a word
All SIC addresses are a byte address and words are
addressed by the location of the lowest number byte
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
8. 1 BIT 1 BIT 1 BIT 1 BIT 1 BIT 1 BIT 1 BIT 1 BIT
b7 b6 b5 b4 b3 b2 b1 b0
1 BYTE
1 BYTE = 8 BITS
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
1 BYTE 1 BYTE
1 BYTE
3 BYTE= 1 WORD
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
9. 2. REGISTER
There are five registers all of which have a specified
special use
MNEMONICS CODE SPECIAL USE
A 0
Accumulator Used For
Arithmetic Operations.
X 1 Index Register
L 2 Linkage Register
PC 8 Program Counter
SW 9
Status Word Includes A
Variety Of Information
Including Condition Codes
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
10. 3. Data Formats
Integers are stored has 24 bit binary number
No floating points variables in SIC.
Characters are stored using 8 bits ASCII codes
4. Instruction Formats
All machine instructions on the standard versions of
SIC are 24 bits format.
the flag bit ‘x’ is used to indexed addressing mode
OPCODE X ADDRESS
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
11. 5. ADDRESSING MODES
There are two types of addressing modes indicated by
setting the flag bit ‘X’ in the instruction
Mode Indication Target Address
Direct Mode X=0 TA= Address
Indexed Mode X=1 TA= Address+[X]
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
12. 6. Instruction Set
SIC provides basic set of instructions
load and storage registers.
Integer arithmetic operations.
All automatic operations involve Register A and word in the
memory with the result being left in the register.
7. Input & Output
Input and output are performed by transferring 1bite to or from
the rightmost 8 bit of register A.
There are three input and output instructions each of which
specifies the device code has an operand
a) The test device: instructions does so whether the address
address to device is ready to send or receive data
b) read data in this sequence should be repeated for
each data to be read or written.
c) write data
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
13. SIC/XE [Simplified Instruction
Computer Extended]
Design to list the most commonly encountered habit
features and the concepts of while avoiding most of the
idiosyncrasies often that are found in real machines
The SIC/XE architecture depends upon on the following
features:
1. Memory
2. Register
3. Data Formats
4. Instruction Formats
5. Addressing Modes
6. Instruction Set
7. Input and output
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
14. 1. MEMORY
The size of the memory that can be addressed = 220
=1MB
Memory consists of 8 bits that makes one byte
Any three consecutive bytes form a word
All SIC/XE addresses are a byte address and words are
addressed by the location of the lowest number byte.
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
15. 2. REGISTER
There are nine registers all of which have a specified special
use
MNEMONICS CODE SPECIAL USE
A 0 Accumulator Used For Arithmetic Operations.
X 1 Index Register
L 2 Linkage Register
PC 8 Program Counter
SW 9
Status Word Includes A Variety Of Information
Including Condition Codes
B 3 Base Register; used for addressing
S 4 General Purpose Register
T 5 General Purpose Register
F 6 Floating Point Accumulator (48 bits)
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
16. 3. Data Formats
The exponent has value ‘e’ and the fraction has value
‘f’, the absolute value of the number is represented as
f*2(e-1024)
S=0-> positive
S=1->negative
Fraction->value between 0 to 1
Exponent-> value between 0 to 2047
Total data format is 48bits
S Exponent Fraction
1 bit 11 bit 36 bit
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
17. 4. Instruction Formats
a. Format 1 (I byte)
b. Format 2 (2 byte)
c. Format 3 (3 bytes)
d. Format 4 (4 bytes)
Opcode
8 bits
Opcode Register1 Register2
8 bits 4 bits 4 bits
Opcode n i x b p e
displaceme
nt
6 bits 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 12 bits
Opcode n i x b p e Address
6 bits 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 20 bits
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
18. 5. Addressing Mode
n i x b p e Addressing modes
0 1 Immediate Addressing Modes (#)
1 0 Indirect Addressing Modes (@)
1 1
Not immediate not indirect Addressing
Modes or simple addressing mode
1 Indexed Addressing Modes
0 Direct Addressing Modes
0 1
Program Counter Relative Addressing
Modes
1 0 Base relative Addressing Modes
0 0 Simple Addressing Modes
1 1 Invalid Addressing Modes
0 Format 3
1 Format 4
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
19. 6. Instruction Set
SIC/XE provides all set of instruction set similar to SIC
standard version
In addition floating point arithmetic operations they
include register-to-register operations [ADDR, SUBR,
MULR, DIVR]
SVC (Supervisor Call)- specially provided in SIC/XE to
generate an interrupt used to communicate with
operating system.
7. Input & Output
There are I/O channels that can be used to perform I/O
while CPU is executing other instructions.
It also provides same set of I/O that of SIC standard
version provides
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
20. Target Address Calculation
If b=006000 H, p=003000 H and x=000090
H
1. 032600 H
0000 0011 0010 0110 0000 0000
TA = PC+ displacement
= 003000+600
=003600 H
0000 00 1 1 0 0 1 0 0110 0000 0000
opcode n i X B P E displacement
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
21. Target Address Calculation
If b=006000 H, p=003000 H and x=000090
H
2. 03C300 H
0000 0011 1100 0011 0000 0000
TA = b+x+displacement
= 006000+000090+300
=006390 H
0000 00 1 1 1 1 0 0 0011 0000 0000
opcode n i x b p e displacement
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
22. HOME WORK
3. 022030 H
4. 010030 H
5. 003600 H
6. 0310C303 H
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
23. Examples program in SIC & SIC/XE
Write SIC & SIC/XE program on Arithmetic operation involving APLHA+INCR-
1=BETA, GAMMA+INCR-1=DELTA
SIC PROGRAM
LDA APLHA
ADD INCR
SUB ONE
LDA BETA
STA BETA
LDA GAMMA
ADD INCR
SUB ONE
LDA DELTA
STA DELTA
.
.
.
ONE WORD 1
ALPHA RESW 1
BETA RESW 1
GAMMARESW 1
DELTA RESW 1
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
24. SIC/XE PROGRAM
LDS INCR
LDA ALPHA
ADD S,A
SUB #1
STA BETA
LDA GAMMA
ADDR S,A
SUB #1
STA DELTA
.
.
.
ALPHA RESW 1
BETA RESW 1
GAMMA RESW 1
DELTA RESW 1
INCR RESW 1
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
25. HOME WORK
Write SIC & SIC/XE program on Arithmetic operation
involving
BETA=ALPHA-INCR+2
DELTA=GAMMA-INCR+2
INFRA=BETA+DELTA
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
26. Write SIC & SIC/XE program on string operation involving
the string “system software”
SIC PROGRAM
LDX ZERO
MOVECH LDCH STR1,X
LDCH STR2,X
TIX FIFTEEN
JLT MOVECH
.
.
.
STR1 BYTE C ‘system software’
STR2 RESB 15
ZERO WORD 0
FIFTEEN WORD 15
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
27. SIC/XE PROGRAM
LDT #15
LDX #0
MOVECH LDCHSTR1,X
LDCHSTR2,X
TIXR T
JLT MOVECH
.
.
.
STR1 BYTE C ‘system software’
STR2 RESB 15
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
29. Assemblers
An assembler is a program that converts an assembly
language program to its equivalent object program.
The assembler accepts source program written in
assembly language as the input and produces object
program as the output.
The object program consists of:
object code (also called machine code) which are
nothing but code for the instructions given to the
microprocessor
It also contains instructions to the loader.
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
30. Assembler Function
5 COPY START 1000
10 FIRST STL RETADDR
FIG. 2.1 PROGRAM EXAMPLE
Figure 2.1 shows the assembly language for the basic
question of SIC.
The line numbers are for reference only and are not the
part of the program
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
31. In addition to the mnemonics machine instructions may
have assembler directives
1. Start : Specifies name and starting the address of the
program
2. End : indicates the end of the source program and specify
the first executable instruction in the program
3. BYTE : generate the character or hexadecimal constant,
occupying has many bytes has needed to represent
constant
4. Word: generator one word integer constant
5. RESB : reserve the indicated number of bytes for the data
area
6. RESW: reserved the indicates the number of words for data
area.
The main routine calls the subroutine to read the record or
write the record or execute the instructions.
Assembler Directives
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
32. SIC Assemblers
The translation of the source program to object code
that requires us to accomplish the following functions
1. Convert the mnemonic operation codes to there
machine level language equivalent. Ex: STL to 14
2. Convert the symbol operand to their equivalent
machine address. Ex: writing location number
3. Build the machine instruction in the proper format.
4. Convert the data constant specified in their source
program into their internal machine representation
5. Write the object program and assembly listing
The details of the formats are arbitrary away work
information obtained in these records must be present in
the object program
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
33. Header Record
Col 1 H
Col 2-7 Program name
Col 8-13 Starting address of the object program
(hexadecimal)
Col 14-19 Length of the object program in bytes
(hexadecimal)
Text Record
Col 1 T
Col 2-7 Starting address for object code in this text record
(hexadecimal)
Col 8-9 Length of object code in this text record in bytes
Col 10-69 Object code represented in hexadecimal ( 2
columns per bytes of object code)
End Record
Col 1 E
Col 2-7 Address of the first executable instruction in
object program. (hexadecimal)
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
34. Data structures used in the design
of assemblers
1. OPTAB
2. SYMTAB
3. LOCCTR
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
35. OPTAB :-Operation Code Table
• It must contain at least the mnemonic operation code
and its machine language equivalent.
• During Pass 1: when a statement is read from the table
or file, the mnemonic is searched in OPTAB, if it is
present its length is obtained from OPTAB and
location counter (LOCCTR) is been updated by the
length of the instruction if not present then it is not
valued mnemonic.
• During pass2: when the mnemonic is searched in
OPTAB, its OPCODE and the corresponding format is
read. Using the OPCODE and the format the
assembler converts the language instructions to its
equivalent object code.
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
36. SYMTAB: Symbol Table
• SYMTAB includes the name and the value for each
label in the source program together with flags to
indicate error condition
• During Pass1 of the assembler tables are entered into
the STMTAB as they are encountered in the assembler
instruction
• Since the entries are rarely deleted from their table
efficiency of deletion is not an important issue.
• For this reason pass1 usually writes an immediate file
that contains each source program statements
together with its assigned address errors indicating
indicators etc
• This file is used as input to the past 2.
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
37. LOCCTR: Location Counter
• LOCCTR is initialized to the beginning address
specified in the start
• After each source statement is processed, the length of
the assembled instruction or the length of data area is
added to LOCCTR.
• Thus, LOCCTR Is used to assign address to each
instruction.
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
40. Rules:
1. Find the length of each instruction
a) An instruction that has register as first operand = 2
bytes.
b) An instruction that has two operand = 2 bytes
c) An instruction that has symbol as operand = 3 bytes
d) An instruction that has RSUB has length of= 3 bytes
e) An instruction preceding with ‘+’ has length of = 4
bytes
2. Find the length of data area.
3. Initialize LOOCTR to 0000 and start updating
LOCCTR by adding the length of each instruction or
length of data area, when we encounter a label enter
the label and current LOCCTR into symbol table.
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
41. 4. Label length calculation
a) WORD= add 3 to LOCCTR
b) RESW = add(3* value of operand) to LOCCTR
c) RESB= add value of operand to LOCCTR
d) BYTE= find the length of constant in bytes add into LOCCTR
5. Create SYMTAB for labels.
6. Calculate the object code of each instruction based on location,
length and addressing modes with specified instruction formats.
7. Generate the object program using all three records
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
42. LOC LENGTH LABEL MNEMONIC OPERAND OBJECT CODE
SUM START 0
FIRST LDX #0
LDA #0
+LDB #TABLE2
BASE TABLE2
LOOP ADD TABLE, X
ADD TABLE2, X
TIX COUNT
JLT LOOP
+STA TOTAL
RSUB
COUNT RESW 1
TABLE RESW 2000
TABL2 RESW 2000
TOTAL RESW 1
END SUM
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
43. LOC LENGT
H
LABEL MNEMON
IC
OPERAND OBJECT CODE
SUM START 0
3 FIRST LDX #0
3 LDA #0
4 +LDB #TABLE2
BASE TABLE2
3 LOOP ADD TABLE, X
3 ADD TABLE2, X
3 TIX COUNT
3 JLT LOOP
4 +STA TOTAL
3 RSUB
3 COUNT RESW 1
1770 TABLE RESW 2000
1770 TABL2 RESW 2000
3 TOTAL RESW 1
END SUM
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
44. LOC LENGTH LABEL MNEMONIC OPERAND OBJECT CODE
0000 SUM START 0
0000 3 FIRST LDX #0
0003 3 LDA #0
0006 4 +LDB #TABLE2
BASE TABLE2
000A 3 LOOP ADD TABLE, X
000D 3 ADD TABLE2, X
0010 3 TIX COUNT
0013 3 JLT LOOP
0016 4 +STA TOTAL
001A 3 RSUB
001D 3 COUNT RESW 1
0020 1770 TABLE RESW 2000
1790 1770 TABL2 RESW 2000
2F00 3 TOTAL RESW 1
2F03 END SUM
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
45. TOTAL ADDRESS =LOCCTR+STARTING ADDRES
=2F03+0000
=2F03 H
SYMTAB:
LABEL LOC
FIRST 0000
LOOP 000A
COUNT 001D
TABLE 0020
TABLE2 1790
TOTAL 2F00
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
46. LOC LENGTH LABEL MNEMONIC OPERAND OBJECT CODE
0000 SUM START 0 0
0000 3 FIRST LDX #0 058000 H
0003 3 LDA #0 010000 H
0006 4 +LDB #TABLE2 69101790 H
BASE TABLE2
000A 3 LOOP ADD TABLE, X 1BA013 H
000D 3 ADD TABLE2, X 1BC000 H
0010 3 TIX COUNT 2F200A H
0013 3 JLT LOOP 3B2FF4 H
0016 4 +STA TOTAL 0F102F200 H
001A 3 RSUB 4F0000 H
001D 3 COUNT RESW 1
0020 1770 TABLE RESW 2000
1790 1770 TABL2 RESW 2000
2F00 3 TOTAL RESW 1
2F03 END SUM
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
48. LOC LENGTH LABEL MNEMO
NIC
OPERAND OBJECT CODE
COPY START 1000
CLOOP +JSUB RDREC
LDA LENGTH
COMP ZERO
JEQ EXIT
J CLOOP
EXIT STA BUFFER
LDA THREE
STA TOTAL_LENGTH
RSUB
BUFFER RESW 100
EOF BYTE C ‘EOF’
ZERO WORD 0
THREE WORD 3
LENGTH RESW 1
TOTAL_LENGTH RESW 1
RDREC LDX ZERO
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
50. Literals
A literals is a constant specified in a operand field of an
instruction.
Literals should be enclosed within a pair of a single
quotes and it must be preceded with symbol =
Ex:
For decimal ex: LDA =4095
For hexadecimal ex: TD =‘X’
For string ex: LDA =C‘EOF’
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
51. Advantages of Literals
Literals will receive the programmer from defining a
constant else where in the program within the help of
the assembler directive BYTE or WORD and make a
label for it.
When the programmer uses a literal in the operand
field of the instruction has shown LDA =X‘FFFF’ the
assembler will define all the literals constant at the end
of the program i.e., once the END directive is been
detected
Assembler gathers information of all the literals in the
first pass and insert them into the end of the program
and uses the addresses to assemble the instruction in
the second pass
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
52. LTORG
It is possible to insert the literals in the middle of the
object code also with the help of the assembler
directive LTORG, is an assembler directive using which
we can tell the assembler to define and insert the
liberal values along with their addresses at the point
where LTORG is present.
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
53. So to place the definition of literals nearer to the
instruction which references them we use assembler
directive
By using LTORG we can avoid the format 4, which will
take you just storage area
Line no Label Mnemonic Operand Comment
5 COPY START 0
. . .
25 LDA =C ‘EOF’ EOF is defined at line no 25
. . .
50 LTORG
EOF will be inserted from the line no 50 after
reading LTORG
. . .
70 LDA =C ‘ABC’ ABC is defined at line no 75
90 END COPY
ABC will be inserted from the line no 90 after
reading END
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
54. Handling Literals by assemblers
Literals are handled by assemblers using a basic data
structures called literal table “LITTAB”.
During Pass1
If literal is encountered during scanning, the assembler
searches LITTAB, if present no problem, If not the literal
should be added.
When the assembler directive such as LTORG or END is
encountered, the assembler makes a scan of the literal
table. The first undefined address is filled with value
obtained from LOCCTR.
As address are assigned the location counter is updated
to reflect the no of bytes occupied by each literal.
NAME VALUE LENGTH ADDRESS
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
55. EX: LOC MNEMONIC OPERAND
001A LDA =C ‘EOF’ ----------------------------- 1
…
…
LTORG ------------------------------------------------------- 2
…
Assuming when LTORG is encountered,
Let LOCCTR=002D
1. When the literal =C ‘EOF’ is encountered, it is entered into the literal table
as shown
2. When LTORG is encountered assume LOCCTR value=002D. This value is
entered as the address of the literal in the literal table as
NAME VALUE LENGTH ADDRESS
=C ‘EOF’ 454F46 3 BYTES 002D
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
56. 3. LOCCTR is updated as LOCCTR=LOCCTR+3=002D+3=0030
During Pass2
When a literal is encountered its address is obtained from the
literal table and instruction will be assigned using this address
and object code is generated as
DISPLACEMENT = ADDRESS OF LITERAL-PC
= 002D-001D (PC VALUE AFTER LDA =C ‘EOF’)
= 0010
OPCODE=00, N=1, I=1, X=0, B=0, P=1, E=0, FORMAT 3
0PCODE 6 BITS N I X B P E DISPLACEMENT 12 BITS
0000 00 1 1 0 0 1 0 0000 0001 0000
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
57. Symbol Defining Statements
The programmer can define the symbols and specify
the values associated with the symbols using the
following two assembler directives
1. EQU Ex: MAX_LEN EQU 1024
1. ORG Ex: ORG 3000
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
58. 1. EQU
The assembler directive using which we can tell the
assembler to assign the values of the labels.
Syntax Symbol EQU Value
Ex: MAX_LEN EQU 1024
The symbol directive specifies the symbol entered into
the SYMTAB and assigns the values specified in the
operand to the symbol
The value may be constant or an expression.
Normally EQU is used to replace the constant in the
program with the symbol names and it is used for
improving the readability of the program.
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
59. Ex: MAXLEN EQU 4096
+LDT #MAXLEN
During assembly of the above program segment, when
EQU is encountered the pass 1 assembler enters the
MAXLEN into the symbol table SYMTAB with the
value 4096.
During pass2 while assembling +LDT instructions,
assembler searches the SYMTAB for the symbol
MAXLEN and obtains its value. This value is used to
assemble the current instructions and generate the
object code
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
60. 2. Org
is a assembler directive using which we tell the assembler
was to indirectly assign the values to symbols by initiating
LOCCTR with the new value
It allows the assemblers to reset the PC value to the
specified value
When ORG is encountered the assembler initialises the
LOCCTR to the specified value.
ORG will affect the value of all the labels defined until next
ORG is encountered.
Syntax: ORG VALUE
EX: ORG 3000
About statement initially is the LOCCTR with the value of
3000
Using ORG we can also tell the assemblers to assemble the
new LOCCTR.
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
61. COPY START 1000
FIRST STL RETADDR
. . .
. . .
ORG 3000
SECOND STA LENGTH
Assembler assigns 1000 to LOCCTR and assigns address to
each instruction in the program based on length.
When ORG 3000 is encountered the LOCCTR value is
initialized to 3000 and assigns from this point onwards.
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
62. Expression
Expressions are allowed in operand field, assembler
evaluates the expression and produces a single
operand address or value.
There are two types of expression
1. Relative expression
2. Absolute expression
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
63. Relative Expression
The expression that are used in the operand field of the
instructions normally contain the symbols defined as
labels. As the current location changes the value of the
corresponding label changes.
The expression whose value changes relative to the
current location value are called as relative expressions.
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
64. COPY START 0000
0000 . . . . . .
. . . . . . . . .
. . . . . . . . .
0050 BUFFER RESB 05
0055 BUFFEND EQU *
MAXLEN EQU BUFFEND
Starting address in 0000, hence BUFFER is 0050, if starting
address was from 1000, then BUFFEND is 1050.
The expression * indicates the current location value is used
Now, BUFFER is 0050, then BUFFEND is 0055
If, BUFFER is 1050, then BUFFEND is 1055
Value of operand with BUFFEND depends on location of the
starting address, hence operand with BUFFEND becomes in
relative terms Prof. Shweta Nirmanik, Dept. CSE, REC HKT
65. Absolute Expression
Expression that contains only absolute terms is an absolute
expression
Ex: 1. Constant values:
MAXLEN EQU 1024
MAXLEN EQU 1024+5
2. Absolute expression may contain relative terms
MAXLEN EQU BUFFEND-BUFFER
if starting address is 0000 then,
BUFFER=0050 and BUFFEND=0055, MAXLEN=0055-0050 = 05
if starting address is 1000 then,
BUFFER=1050 and BUFFEND=1055, MAXLEN=1055-1050 = 05
In both the above conditions the value of MAXLEN is same i.e., 05. hence MAXLEN
is absolute expression.
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
66. Program Blocks
Features resulting in the creation of the several independent parts of the object
program maintain their identity and handle the separated by the loader.
Program blocks are used to refer to segments of the code that are rearranged within
the single object program unit and the control section to refer the segment that are
translated into independent object program units.
The assembler directive USE indicates which portion of the source programmer
belongs to various blocks
At the beginning of the program of statements are assumed to be the part of the
unnamed (default) block
If no USE statement are included the entire single program belongs to this single
block.
The Example provided in the text book (page number 83) USE statement on line
number 92 signals the beginning of the block name the CDATA
Source statements are associated with its block until you statement on line number
103 which begins the block named CBLKS
The USE statement may also indicate the continuation of the previously begin block
the statement online number 123 resume default block. Thus statement on line
number 183 resumes the block named the CDATA
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
68. During pass 1
Separate LOCCTR for each program block is created
LOCCTR is initialised to zero.
Each level in the program is assigned as an address that is
relative to the start of the block that contains it
At the end of the pass 1, the latest value of the location
counter for each block indicates the length of that block
Assembler assigns to each block a starting address in the
object program
During pass 2
The assembler needs the address for the each symbol
relative to start of the object program
This is easily formed from the information in the SYMTAB
The column location / block shows the relative addresses
assigned to each source line and the block number
indicating which program blocks is involved
0= default block, 1=CDATA, 2=CBLKS
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
69. At the end of the pass 2 the assembler will construct a
table that contains the starting address to length of all
the blocks
Block name Block no. Address length
Default 0 0000 0066
CDATA 1 0066 000B
CBLKS 2 0071 1000
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
70. Consider the below statement
20 0006 0 LDA LENGTH 032060 --------1
SYMTAB shows the value of the operands has a relative
location 0003 within the program block 1
The starting address of CDATA is 0066
The desired target address (LENGTH) for this instruction is
TA= 0003+ 0066=0069
Thus the instruction to be assembled with the program
counter relative addressing mode
Opcode =LDA=00, Format 3, n=1, i=1, x=0, b=0, p=1, e=0,
displacement= TA-PC= 0069-PC.
The PC contains the address 0009 of the following
instruction in line number 25
displacement= TA-PC= 0069-PC=0069-0009=0060.
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
72. Assembler Design Options
One Pass Assembler: these assemblers are used when
it is necessary or desirable to avoid a second pass over
the source program.
Multi Pass Assembler: an extension to the two pass
logic that allows an assembler to handle forward during
symbol definition.
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
73. One Pass Assembler
The assemblers that makes only one pass while converting
from assembly language to the source language or viva versa
is called single pass or one pass assembler
Main problem in trying to assemble a program in one pass
involves forward referencing
It easy to eliminate the forward reference to the data items
just by defining of the symbols in the source program before
they are referenced
To reduce the size of the problem many one pass assembler
do probability for references of data items.
There are mainly two types of one pass assembler
1. Producers of that caused directly in the memory for
immediate instruction
2. Produces object code in the memory for immediate
execution
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
74. Produces object code in the memory for immediate
execution
No Object code is written out and no loader is needed this kind of
load and go assembler are useful in object oriented programming
development and testing
A load-and-go assembler avoid the overheadof a writing the object
program out and reading it back in.
Object program is produced in memory rather than being written
out on the secondary storage. Thus the handling of forward
reference is less difficult
The assembler simply generates the object code instructions as it
scans the source program.
The samples were used as an operand is entered into the symbol
table the entry is flagged to indicate that the symbol is been
defined
Undefined symbol is added into a list of a forward reference is
associated with the symbol table entry.
When the definition for the symbol is been encountered for the
forward reference list for that symbol is a scanned and the proper
address is inserted into any instruction previously generated
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
78. Procedures the usual kind of object program for later
execution
1. One pass assembler that produces object program has the output
of an used are often used on the system where the external
working storage devices are not available.
2. One pass assembler that produces object program follows a
strictly different procedure from that of the previously described
3. Forward References are entered into a list as before, however the
definition of the symbol is encountered instruction that made
the forward reference to that symbol or may no longer be
available in the memory for modification
4. In General, they will already have been written out as the part of
the text record in this object program
5. In this case the assembler must generate text record with the
correct operand address.
6. When the program is loaded this address will be inserted into the
instructions by the action of the loader
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
79. Multi - Pass Assembler
Ex: ALPHA EQU BETA
BETA EQU DELTA
DELTA EQU 1
Assemblers that make only two sequential passes over the source
program cannot resolve such a sequence of definitions.
Some assemblers are designed to eliminate the need for such
restrictions the general solution is a strong multi pass assemblies
that can make as many as passes as needed to produce the
definition of the symbols
It is not necessary for such an assembler to make more than two
passes over the entire program instead the portion of the
program that in was for references in the simple definitions are
saved during pass 1
Additional Passes through these stored definitions are made as
assembly progresses. This is process followed by a normal pass 2
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
80. EX:
1. HALFSZ EQU MAXLEN/2
2. MAXLEN EQU BUFEND-BUFFER
3. PREVBT EQU BUFFER-1
4. BUFFER RESB 4096
5. BUFFEND EQU *
MAXLEN has to be defined the HALFSN cannot be
computed
The defining expression is HALFSN is stored in the
symbol table
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
81. HALFSZ &1 MAXLEN/2
MAXLEN *
A
Fig: Example of multi pass assembler operations
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
82. BUFEND *
HALFSZ &1 MAXLEN/2
MAXLEN &2 BUFEND-BUFFER
BUFFER *
B
Fig: Example of multi pass assembler operations
MAXLEN
MAXLEN
HALFSZ
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
83. BUFEND *
HALFSZ &1 MAXLEN/2
PREVBT &1 BUFFER-1
MAXLEN &2 BUFEND-BUFFER
BUFFER *
C
Fig: Example of multi pass assembler operations
MAXLEN
MAXLEN
HALFSZ
PREVBT
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
84. BUFEND *
HALFSZ &1 MAXLEN/2
PREVBT 1033
MAXLEN &1 BUFEND-1034
BUFFER 1034
D
Fig: Example of multi pass assembler operations
MAXLEN
HALFSZ
Prof. Shweta Nirmanik, Dept. CSE, REC HKT
85. BUFEND 2034
HALFSZ 800
PREVBT 1033
MAXLEN 1000
BUFFER 1034
E
Fig: Example of multi pass assembler operations
Prof. Shweta Nirmanik, Dept. CSE, REC HKT