2. 11/17/2019 2
Arithmetic and Logic Unit
• The ALU is at the heart of the CPU
– Does math and logic
• The ALU is primarily involved in R-type instructions
– Perform an operation on two registers and produce
a result
• Where is the operation specified?
– The instruction type specifies the operation
– The ALU will have to be controlled by the
instruction opcode
4. ALU - Logic Operations
0
1
A
B
Operation
Result
2-to-1 Mux
If Operation = 0, Result = A • B
If Operation = 1, Result = A B
Start out by supporting AND and OR operations
AB
A+B
Two operands, two results.
We need only one result...
The Operation input comes from logic that looks at the opcode
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7. Adding to our ALU
CarryIn
CarryOut
ALU
A
B
Cout
Cin
Result
Cin
Cout
Op (2 bits)
Operation Function
00 A • B
01 A B
10 A + B
+
(Op is now 2 bits)
Add an Adder
Connect CarryIn (from previous bit) and CarryOut (to next bit)
Expand Mux to 3-to-1 (Op is now 2 bits)
0
1
Operation
Result
A
B
2
0
1
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8. 11/17/2019 8
1-bit & 32-bit ALU
• Connect to common
Operation controls
– Now we can do 32-bit
AND and OR operations
• Stack 32 of our 1-bit ALU’s
together
– Each one gets one bit
from A and one from B
• Connect Cout’s to Cin’s
– Now, 32-bit adds will
work
– Note: Carry will ripple
through the stages, one
at a time
• Ripple-Carry Adder
9. Subtracting
0
1
B
0
1
A
Operation
Result
+ 2
CarryIn
CarryOut
BInvert
For subtraction:
Set CarryIn of LSB to 1,
Set BInvert to 1
• Add an inverter, and a signal
BInvert to get B
• Now, how about that +1?
– CarryIn to LSB is unused
(always zero)
– Set it to 1!
• Subtraction just sets
BInvert and Cin to 1
B
• Our ALU can add now, but
what about subtraction?
• To compute A - B, we can
instead compute A + (-B)
• In 2’s complement,
-B = B + 1
Set to 1 for LSB
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11. Support for SLT
• A<B is equivalent to (A - B) < 0
• Subtract B from A
– If the result is negative,
then set LSB of Result to
‘1’, all others to ‘0’
– The result is negative if the
MSB after the subtraction
is ‘1’ (Two’s complement)
Result
0
1
A
Operation
+ 2
B
CarryIn
CarryOut
0
1
BInvert
Less
We’re going to have to do something different
for the MSB and the LSB
• We need to support the SLT
operation
– Set Result to
0000 0000 0000 0000
0000 0000 0000 0001 if A <B
0
1
2
3
Less will be ‘0’ for bits
1-31, special for bit 0
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12. That tricky MSB
• To properly execute the
SLT, we need to Set the
LSB if the MSB is ‘1’
– (After a subtraction)
OverFlow
Set
0
1
A
Operation
Result
+ 2
B
CarryIn
CarryOut
0
1
BInvert
3
Less
MSB Only
• Can’t use the ‘Result’ of the
MSB
– Op will set the Mux to
the ‘Less’ Field
– Bring out the adder
output directly: ‘Set’
• Also, we need to check for
overflow
– Overflow if Cin to MSB
is different from Cout of
MSB
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21. 11/17/2019 21
Instruction Format
• Should all MIP instructions be of the same format?
• lw $t0, 32($s3)
• Could specify constant using the 5-bit rt field?
• Design Principle 3:
– Good Design demands good compromises
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MIP Instruction Formats
• R-format
• I-format
– used by data transfer instructions
– Opcode 6-bit
– rs 5-bit
– rt 5-bit
– address 16-bit
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Instruction Format
• Multiple formats complicate hardware
• Complexity reduced by keeping formats similar
– R-format & I-format first three fields same
– Address field spans over three fields
– Opcode differentiates between formats
27. Logical Operations
• Operation on fields of bits within a word or even on
individual bits.
– Shift left - sll
– Shift right – srl
– AND – and
– OR – or
– NOR – nor
– AND immediate – andi
– OR immediate - ori
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28. Shifts
• sll : move all the bits in a word to the left , filling the emptied
bits with 0s
– Eg. $s0 contains
0000 0000 0000 0000 0000 0000 0000 1001two = 9ten
and the instruction shift left by four will result in
0000 0000 0000 0000 0000 0000 1001 0000two = 144ten
sll $t2,$s0,4 # reg $t2 = reg $ s0 << 4 bits
op rs rt rd shamt funct
0 0 16 10 4 0
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29. Other logical operations
• Shift right
– srl $t2,$s0,4 # reg $t2 = reg $ s0 << 4 bits
• AND
– and $t0,t1,t2 # reg $t0 = reg $t1 & reg $t2
• OR
– or $t0,$t1,t2 # reg $t0 = reg $t1 | reg $t2
• NOT
– nor $t0,$t1,$t3
# reg $t0 = ~ ( reg $t1 | reg $t2)
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32. 11/17/2019 32
Branches: PC-relative Addressing
• Use I-Format
opcode rs rt immediate
opcode specifies beq v. bne
Rs and Rt specify registers to compare
What can immediate specify?
o Immediate is only 16 bits
o PC is 32-bit pointer to memory
o So immediate cannot specify entire address to
branch to.
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Branches: PC-relative Addressing
• How do we usually use branches?
– Answer: if-else, while, for
– Loops are generally small: typically up to 50
instructions
– Function calls and unconditional jumps are done
using jump instructions (j and jr), not the
branches.
• Conclusion: though we may want to branch to
anywhere in memory, a single branch will generally
change the PC by a very small amount.
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Branches: PC-relative Addressing
• Final calculation:
– If we don’t take the branch:
Pc = pc + 4.
– If we do take the branch:
PC = (PC + 4) + (immediate * 4).
– Observations.
• Immediate field specifies the number of words
to jump, which is simply the number of
instructions to jump.
• Immediate field can be positive or negative.
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J-Format Instructions
For branches, we assumed that we won’t want to branch too far, so
we can specify change in PC.
For jumps (j ), we may jump to anywhere in memory.
Ideally, we could specify a 32-bit memory address to jump to.
Unfortunately, we can’t fit both a 6-bit opcode and a 32-bit address
into a single 32-bit word, so we compromise.
Define ‘fields’ of the following number of bits each:
6 bits 26 bits
opcode target address
As usual, each field has a name:
Key Concepts
1. Keep opcode field same as R-format and I-format for consistency.
2. Combine all other fields to make room for target address.
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J-Format Instructions
• We can specify 28 bits of the 32-bit address, by using WORD
address.
• Where do we get the other 4 bits?
– By definition, take the 4 highest order bits from the PC.
– Technically, this means that we cannot jump to anywhere in
memory, but it’s adequate 99.9999% of the time, since
programs aren’t that long.
– If we absolutely need to specify a 32-bit address, we can
always put it in a register and use the jr instruction.
• Summary:
– New PC = PC[31..28]|| target address (26bits)|| 00
– Note: II means concatenation
4 bits || 26 bits || 2 bits = 32-bit address
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Instruction Format
Instruction Format op rs rt rd shamt funct
beq I 4 reg reg address
bne I 5 reg reg address
slt R 0 reg reg reg 0 42
j J 2 address
jr R 0 reg 0 0 0 8
