1. RESUME
Phone no: 09703488083
Madhu Venkateswarlu B.
E-Mail:madhubandela786@yahoo.com
FPGA design Engineer
Objective:
To put optimized efforts in achieving the organization’s mission and pursue a growth oriented
career along with immense interest in swiftly developing electronics technology and like to be part of
innovative solutions for growing demands in various industries such as power transmission, defense,
security and consumer electronics.
Professional Summary:
• 4.3 years of experience in carrying out FPGA based Design, Development and Testing.
• Expertise in carrying out FPGA based designs with IP core usage Chipscope based
debugging and applying timing constraints.
• Worked on SPARTAN6,Virtex5, Virtex6 , Artix7 and Virtex7 FPGAs
• Experienced in carrying out on-board debugging based on schematic design.
• Knowledge in RTL coding verification using Test benches.
• Carrying out Microblaze and PowerPC based designs and developed customized drivers for
various communication and memory modules using Xilinx based FPGA.
• Good knowledge for various communication modules such as RS232, RS422, Ethernet (PHY
using MII, and GMII) using EDK and SDK.
• Development of Interface drivers for various High Speed analog modules such as DAC (upto
500MSPS) and ADC (upto 500MSPS) for data acquisition.
• High level hardware and software debugging using oscilloscopes, logic analyzers and
spectrum analyzer.
• Knowledge of interfacing with memory modules (DDR2, SDRAM and SRAM) using EDK,
SDK and MIG tools.
• Knowledge in preparing Design documents in AS9100 Rev. C standard from Initial Stage to
final stage
• Participated in Environmental test like Vibration, CATH, BUMP, and Thermal Cycling.
Experience:
Worked as FPGA/RTL design Engineer in Vrinda Technologies Pvt ltd from 19th Jan 2011
to 2nd
June 2015 having 4.3 years experience in FPGA based designs for customized boards.

2. Educational Qualification:
 Post Graduation: Master of Technology (M.Tech) at GITAM University, Visakapatnam with
72.48% in 2010.
 Graduation: Bachelor of Technology (B.Tech) at SISTAM, Srikakulam in 2008.
Technical Skills:
• Hardware description Languages: Verilog, VHDL and C.
• Debugging Tool: Chipscope (Xilinx).
• Development platforms/Tools: Xilinx 14.7 and 13.1 (ISE, EDK, SDK, Vivado).
ModelSim from Mentor Graphics.
Projects:
Project #6: TDF Processor Board
Client: DLRL
TDF processor board is used for processing, control, and configuration. Two Channels of IF
160MHz will be sampled by 500MSPS ADC. Four channels of ADC with 40MSPS sampling from four
ADCs in the FPGA. Controlling DAC's 1 to 6 from FPGA's for generating threshold/BITE voltages
ranging 0-4V.Controlling Clock Distribution Unit to generate sampling clock for ADC's. Clock
generation (500MHz) of ADC with 1 PPM will be done by using Clock Synthesizer. Rocket I/O
communication shall be established from VIRTEX-6 FPGA on VPX backplane through Backplane
LVDS Buffers. Ethernet PHY interface is provided through VPX Backplane.
Contribution towards project:
1. Role: Team member-FPGA Engineer.
2. Team size: 4
3. Responsibilities:
• Preparation of SDD for FPGA development.
• Generation of UCF for DDR2.
• Designing for DDR2 interface in EDK.
• Prepare software test procedure as per client specifications.
• RTL design for ADC, DAC, LVDS and LVTTL, Testing and integration of all modules
and ESS also.DDR2 implemented in EDK and SDK.
• Interacting with hardware designers for application testing.
• Testing & validating the design.
• Developed saturated video and liner log application by using DAC, ADC and delay.

3. Project #5 EAP Processor Board:
Client: DLRL
EA processor board is based on VIRTEX 5 of FX series which contains 2 PowerPC blocks
PPC1 AND PPC2.PPC1 is having the interface with all the peripherals (FLASH, ETHERNET, SRAM,
DDR2 SDRAM, RS422 and RS232) and PPC2 will be the core processor which communicates with
the PPC1.
Contribution towards project:
1. Developed Platform : Microblaze and PowerPc by using EDK and SDK
2. Role Team member-FPGA engineer
3. Team Size:4
4. Responsibilities:
• Preparation of SDD for FPGA development.
• Integration of memory modules such as SRAM, FLASH, SDRAM, DDR2, SPI FLASH,
Ethernet , DAC in Microblaze using EDK and SDK tools by using standalone
BSP(board support package).
• Parallel FLASH based FPGA booting from SREC boot loader using SDK.
• XMD based debugging in SDK.
• Interacting with hardware designers for application testing.
• Testing & validating the design.
This project also developed in EDK and SDK by using Xilkernel BSP in production level
boards.
Project #4 Evaluation Boards
Client: ANURAG
Evaluation boards mainly used for validating the PLL, TXRX, ZIGBEE boards through
communicate with FPGA boards. In these boards contains three spartan6 FPGAs and one Virtex6
FPGA with configurable PROM, One 10/100Mbps Ethernet controller for LAN communication and
RS232, RS422 for serial communication.SPI connector to communicate with the PLL, TXRX, and
ZIGBEE boards.
Contribution towards project:
1. Role: Team member-FPGA Engineer
2. Team Size: 4

4. 3. Responsibilities:
• Preparation of SDD for FPGA development.
• Development and Execution of System Test Plan Document.
• Design of communication between FPGA and ADC's (HSADC and LSADC) to acquire
samples.
• Implementing gated clocks with Xilinx clock resources (CLKDLL/DCM).
• Design RTL code for RS232 and SPI.
• Interacting with Hardware designers for application testing.
• Testing & validating the design.
• Test individual modules with test benches.
Project #3: Range and Velocity Simulator
Client: RCI
Range and Velocity Simulator board acquires data from GUI need to be processed in DAC
through Ethernet. Output frequencies and delayed output has to be generated according to the
command received from GUI. An application of calculating the Range, Velocity and Acceleration of
the target has been done in the FPGA.
Contribution towards project:
1. Role: Team member-FPGA Engineer
2. Team Size: 4
3. Responsibilities:
• Preparation of SDD for FPGA development.
• RTL design for ADC, DAC and SDRAM (using EDK and SDK) and testing.
• Integration of all modules and testing.
• Interacting with Hardware designers for application testing.
• Testing & validating the design.
Project #2: DRRB
Client: ECIL
The Vertex-5 FPGA based Digital Radar Receiver Board is designed to receive Quad
channel analog inputs from IF Receiver and implement various signal processing algorithms in the
vertex 5 SX FPGA and provide communication interfaces like RS422, RS232.
Contribution towards project:
1. Role: Team member-FPGA Engineer
2. Team Size: 4
3. Responsibilities:

5. • RTL coding for ADC, DAC, Testing and integration of all modules.
• Interacting with Hardware designers for application testing.
• Testing & validating the design.
Project #1: Base Line Information Direction Finding
Client: DLRL
The BLIDF processor unit receives phase from phase correlators and amplitude of video
signals from EDLVA apart from the control signals and frequency data. It uses multiple ADC to serve
the purpose. It has VPX backplane and operates in Industrial Grade temperature range.
Contribution towards project:
1. Role: Team member-FPGA Engineer
2. Team Size: 5
3. Responsibilities:
• Preparation of SDD for FPGA development.
• Developed backplane interface and RTL design for ADCs and VPX interface.
• Testing of all modules and ESS also
• Developed backplane interface and RTL design for ADCs and VPX interface
• Interacting with Hardware designers for application testing.
• Testing & validating the design.
Personal Information:
Name : Madhu Venkateswarlu B
Father’s Occupation : Farmer
Date of Birth : 1st
Dec 1986
Gender : male
Marital Status : Unmarried
Nationality : Indian
Languages Known : English, Telugu and Hindi
Permanent Address : D-No: 1-77, MR Palem, Kadiam mandal, Rajahmundry rural,
Eastgodavari.
Declaration:
I hereby declare that the mentioned information above is true to the best of my knowledge.
Place: Hyderabad Yours Faithfully,
Date: (MadhuVenkateswarlu
B)

6. • RTL coding for ADC, DAC, Testing and integration of all modules.
• Interacting with Hardware designers for application testing.
• Testing & validating the design.
Project #1: Base Line Information Direction Finding
Client: DLRL
The BLIDF processor unit receives phase from phase correlators and amplitude of video
signals from EDLVA apart from the control signals and frequency data. It uses multiple ADC to serve
the purpose. It has VPX backplane and operates in Industrial Grade temperature range.
Contribution towards project:
1. Role: Team member-FPGA Engineer
2. Team Size: 5
3. Responsibilities:
• Preparation of SDD for FPGA development.
• Developed backplane interface and RTL design for ADCs and VPX interface.
• Testing of all modules and ESS also
• Developed backplane interface and RTL design for ADCs and VPX interface
• Interacting with Hardware designers for application testing.
• Testing & validating the design.
Personal Information:
Name : Madhu Venkateswarlu B
Father’s Occupation : Farmer
Date of Birth : 1st
Dec 1986
Gender : male
Marital Status : Unmarried
Nationality : Indian
Languages Known : English, Telugu and Hindi
Permanent Address : D-No: 1-77, MR Palem, Kadiam mandal, Rajahmundry rural,
Eastgodavari.
Declaration:
I hereby declare that the mentioned information above is true to the best of my knowledge.
Place: Hyderabad Yours Faithfully,
Date: (MadhuVenkateswarlu
B)