1. VENKATA RAKESH GUDIPALLI
101 E San Fernando, San Jose, CA. 95112 | Phone # (515)598-6991
Email ID: venkatarakesh.gudipalli@sjsu.edu LinkedIn: https://www.linkedin.com/in/venkata-rakesh-gudipalli-13a35841
SUMMARY
 1 year of hands on experience of Verilog RTL, System Verilog, digital ASIC design, FPGA, computer architecture, FSMs.
 2 years of professionalexperience in OO programming and scripting for automation as software developer at TCS.
 Experience in developing test strategies, test benches, assertions and constraint random test cases in SystemVerilog & UVM.
 6 months of experience with FPGA prototyping and FPGA design tool – Altera Quartus II.
 Project work in designing 2-stage OpAmp using Cadence Virtuoso Schematic and Layout editor.
 Hands on experience of Synthesis,CDC, STA, timing fix, placement and route and low power design.
 Experience implementing JTAG and DFT techniques like D- Algorithm, Scan and BIST.
 6 months of experience and extensive coursework in SoC design and verification, Digital Circuit Design, CPU Architecture,
RFIC Design, ASIC CMOS Design, VLSI Design, Semiconductor device physics,Circuit analysis.
EDUCATION
 MS, Electrical Engineering (EE), San Jose State University, CA, GPA-3.73/4 Dec’16
 B.Tech, Electrical Engineering(EE), JNTU, India, GPA- 3.7/4 Jun’12
SKILLS
 Languages : Verilog, SystemVerilog, JAVA, C, C++, RISC, SQL, SVN, HTML.
 EDA Tools and CAD packages : UVM Methodology,Synopsys VCS, Design Compiler, Cadence Virtuoso Schematic
and Layout Editor, Encounter, Simulink, Spectre, ModelSim, Quartus II, HSPICE.
 Scripting skills : Perl, Java Script, shell-scripting, DC shell.
 Bus Protocols : AMBA APB, AHB, PCI.
PROFESSIONAL EXPERIENCE
Hardware Intern, Finisar Corporation (Jul’16 – Aug’16)
 Analyzed ASICs for their applicability in internal test boards using various bench equipment.
 Developed production and characterization test specifications.
 Tested and characterized test boards and ICs using signal generator, DCA Oscilloscope, Vector Network analyzer & BERT.
 Performed failure analysis and debug on test boards to come up with a solution for the failure.
Systems Engineer, Tata Consultancy Services Ltd.(TCS), India (Dec’12-Dec’14)
 Developed software components with Object Oriented Programming (OOP) in C++ and JAVA.
 Developed the test plans and tested the software components developed by peer developers at unit level (white-box testing).
 Proficient in agile methodology for the implementation of Product Development Life Cycle (PDLC).
 Reported the bugs and documented the observations and coverage.
ACADEMIC PROJECTS
Design of LCD controller [System Verilog, Synopsys VCS] (Feb’16-Apr’16)
 Designed an LCD controller to provide necessary controlsignals to interface directly to color and monochrome LCD panels.
 Designed the systemusing System Verilog,and tested for the functionality.
Hardware Gaussian Noise Generator using Box-Muller method [Verilog, OSU 0.18um, Synopsys VCS, Encounter] (Apr’16)
 Designed 64-bit Gaussian Noise Generator using Box-Muller method and optimized it to work at 500 MHz, 300 MHz and
220 MHz using 2-flag push model of pipelining. Generated clock tree and performed Place & Route using Encounter.
 Implemented SCAN based DFT technique.
 Performed timing analysis after Place & Route using encounterand fixed the long paths and races.
 Developed final test plan and test benches to verify the functionality.
Verification of USB 2.0 IP with UVM Methodology [System Verilog, UVM] (May’16-Present)
 Designing System Verilog UVM Testbenches and environment for verification of USB 2.0 IP.
 Developing testplans and testbenches to test High speed & Full speed operating modes, Suspend & Resume Functionalities.
 Analyzing code coverage & functional coverage for defined cover points.
Design of 7 stage MIPS pipeline simulator [MIPS, C++] (Mar’15-May’15)
 Designed a simulator, which can simulate 32-bit 7-stage pipeline RISC CPU based on MIPS, in C++.
 Implemented forwarding and bypassing in the simulator and branches were predicted not taken for branch hazards.
 Simulation output is a text file with timing of the instruction sequence and final contents ofall registers and memory locat ions.
Pattern Matching Game on an FPGA [Altera Quartus II, CYCLONE II] (May’16)
 Implemented a pattern matching game, which displays a pattern on the 7- segment decoders.
 User will have to enter the number of horizontal and vertical segments in the pattern correctly, to proceed to the next level.
 Used toggle switches and push buttons as inputs,7-segment decoder and LEDs as outputs.
Design of 2-Stage Op-Amp [HP 0.6um, Cadence Virtuoso Schematic & Layout Editor, Spectre, UNIX] (Mar’15-May’15)
 Designed a 2-stage Op-Amp and performed DC, AC, Transient and Noise Analysis.
 Created layout using Virtuoso Layout Editor and then extracted and LVS verified.
 Achieved a gain margin of 61dB, phase margin of 53.6 degrees with a power budget of 5mW.