1. William S. Check Jr.
5241 Bartonsville Road
Frederick, MD 21704
(443) 538-6931 (cell phone)
bill_check@ieee.org
Experience
7/2004 – Present Cadence Design Systems, Inc. Columbia, MD
Staff DesignEngineer
• Behavioral Verilog AMS model generation of analog and digital IP and customer specific
blocks for Incisiv, Verilog XL, Verilog AMS, NC Verilog and Sigrity
• Design of customer specific analog macros using existing IP blocks as well as unique project
specific circuits using Analog Artist. The IP blocks included phase lock loops (PLL), analog
to digital converters (ADC), digital to analog converters (DAC) and crystal oscillators.
• Design of symbol coding/decoding control blocks for RF IC macro.
• Technical project lead responsible for customer interaction, team organization, duty
allocation, project meetings, schedule performance, staged design reviews, floor planning
and tape-out.
• Package and test board design
4/2003 – 7/2004 Meridian Technology Group Lake Oswego, OR
Mixed Signal DesignConsultant
• Credence Systems Corporation – Project lead for a 4 Gbps TSMC 28nm CMOS Serializer /
Deserializer (SERDES) IC for the next generation IMS integrated circuit tester. First silicon
was fully functional.
• Generated top-level schematics and behavioral Verilog model for system level simulation.
• Analyzed package requirements, flip-chip pin out, PCB requirements and specified and
directed the design of an 8 layer organic substrate.
• Simulated the clock and data recovery (CDR) to insure lock and stability.
12/2001 – 3/2003 Accelerant Networks, Inc. Beaverton, OR
Director of Applications and Signal Integrity Engineering
• Managed and directed a 7-person group of field and factory application (FAE) engineers,
signal integrity (SI) engineers and printed circuit board (PCB) layout engineers.
• Conducted customer demonstrations, public seminars, conference presentations (HotChips
and CommDesign) and trade show exhibits.
• Published User Manuals, Quick Start Guides, Application notes, presentations and white
papers using Microsoft Word, Power Point, Excel, Adobe FrameMaker, Distiller and
Acrobat.
• Designed, generated ORCAD schematics, supervised Allegro PCB layout, debugged 14 layer
line and switch card, characterized, documented and demonstrated a 2.5 Terabit evaluation
vehicle for Nortel Networks.
• Designed, debugged, specified the software interfaces and documented a 20 Gb/s evaluation
kit that reduced the cost per kit by 70%.
• Characterized and documented customer backplanes and midplanes to support the sales
force in closing design wins.
• Measured Bit Error Rate (BER) performance of serial traffic at 5 Gb/s and 6.25 Gb/s on
leading systems for Cisco, Nortel, Lucent, Tellabs, Redback, Juniper and others.

2. 1/2000 – 11/2001 Accelerant Networks, Inc. Beaverton, OR
Architect and Principal DesignEngineer
• Architectural design of the transmit and receive data paths for AN5000 using Matlab, Simulink
and Verilog.
• Custom CMOS circuit design of high speed (500 MHz) system interface, data path blocks and
encoder/decoder ROMs fabricated with the TSMC 0.25um CMOS process.
• Schematic capture and simulation with Analog Artist, Spectre and HSIM.
• Simulated gate level logic and generated test vectors using Verilog.
• Interfaced with layout to ensure functionality and speed requirements.
1/1994 – 12/1999 Level One Communications, Inc. Sacramento, CA
Engineering Manager and Chip Architect
• Debug and characterization of a 10/100/1000 Base T Ethernet Transceiver (LXT1000).
• Management responsibilities of a 7 person digital team.
• Coded, simulated and synthesized digital logic using VHDL and Design Compiler (DC) from
Synopsys.
• Extracted timing information using PrimeTime.
• Custom CMOS transistor level design of high speed switching blocks, system I/O cells and
ESD structures for TSMC processes.
• Schematic capture and simulation using Concept and HSPICE.
• Specified and integrated third party tools from Meta Software, Synopsys, and Cadence into
Level One’s ASIC design flow.
• Worked directly with test engineering to develop characterization and production ATE
programs.
12/1986 – 12/1993 Level One Communications, Inc. Sacramento, CA
Staff DesignEngineer and CAD Manager
• CMOS circuit and logic design of mixed signal ICs.
• Standard cell design.
• HSPICE model development.
• FPGA design Prototype development using FPGA and ASIC technology.

3. 1977 – 1985 Additional EmploymentExperience
Xicor, Inc. Milpitas, CA Section Head
Designed, simulated, debugged and patented nonvolatile CMOS electronic potentiometers
and memory cell design used in this product.
Ford Microelectronics, Inc. Colorado Springs, CO Design Specialist
Designed, simulated, supervised layout, debugged and tested the high performance angular
spark controller.
Intel Corporation Chandler, AZ Design Manager
Hands on manager of the team responsible for telecommunication controllers, digital signal
processor and microcontrollers with onboard A/D and D/A.
Education
Lehigh University
BSEE
University of Santa Clara
Electromagnetic Field Theory, Combinational Logic, Programming, Communication Theory,
Finance for Engineering Managers.
Stanford University
Adaptive Systems, Linear Algebra, Fourier Transform and Applications, Digital Filtering and
Digital Signal Processing.
UC Berkley
Differential Circuit Design.
UCLA
Engineering Management, Telecommunications Networking.
Portland State University
Analog Integrated Circuit Design I and I I
Patents
US Patent 5,084,667
Nonvolatile Nonlinear Reprogrammable Electronic Potentiometer.
US Patent 5,059,924
Clock Adapter using a Phase Locked Loop Configured as a Frequency Multiplier with a
Non-integer Feedback Divider.
US Patent 4,668,932
Nonvolatile Reprogrammable Electronic Potentiometer.
Canada 2,002,382
Clock Adapter using a Phase Locked Loop Configured as a Frequency Multiplier with a
Non-integer feedback divider.
US Pending 09/606,785
Cascadable Cross Connect Architecture.
US Filing
System and Method for Providing Variable Rate Sub-Channel Using BLOCK CODE RDS.
US Filing
System and Method for Providing Crosstalk Management for High-Speed Signaling Links.

4. Personal Attributes
Highly energetic, creative self-starter. Strong organization skills with attention to detail, product
quality and schedule deadlines. Professional verbal, written and presentation skills. Exceptional
leadership and management talents. Problem solver possessing the analytic skills necessary to
identify potential product weaknesses and propose probable corrections. Proven interpersonal
skills that maximize productivity of cross functional groups.
Professional Affiliation
IEEE
AOPA