Bca examination 2015 csa

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Assistant Professor (Gajendra Jingar)1
BCA Examination 2015
Computer System Architecture
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Q.1 What is Interrupt?
Ans: Interrupt is a signal send by an external device to the processor, to the processor to
perform a particular task or work. Mainly in the microprocessor based system the interrupts are
used for data transfer between the peripheral and the microprocessor.
TYPES OF INTERRUPTS
The interrupts are classified into software interrupts and hardware interrupts.
• The software interrupts are program instructions. These instructions are inserted at desired
locations in a program. While running a program, lf a software interrupt instruction is
encountered, then the processor executes an interrupt service routine (ISR).
• The hardware interrupts are initiated by an external device by placing an appropriate signal at
the interrupt pin of the processor. If the interrupt is accepted, then the processor executes an
interrupt service routine (ISR)
Q.2 Define Instruction?
Ans: An instruction is a binary pattern designed inside the microprocessor to perform a
specific function. In other words, it is actually a command to the microprocessor to perform a
given task on specified data. Instruction Set. The entire group of theseinstructions are
called instruction set. The instruction set determines what functions the microprocessor can
perform.
Q.3 Difference Between I/O Mapped And Memory Map I/O ?
Ans: Memory Mapped I/O :In this, there is only one address space. Address space is defined
as all possible addresses that microprocessor can generate. Some addresses are assigned to
memories and some to I/O devices. An I/O device is also treated as a memory location and one
address is assigned to it. All the data transfer instructions of the microprocessor can be used for
both memory as well as I/O device. This technique is suitable for small systems.
I/O Mapped I/O : In this addresses assigned to memory locations can also be assigned to I/O
devices. Since the same address may be assigned to a memory location or an I/O device, the
microprocessor must issue a signal to distinguish whether the address on the address bus is for a
memory location or an I/O device.
Q.4 Explain Addressing Format(Instruction Format)?
Ans: The physical and logical structure of computers is normally described in reference manuals
provided with the system. Such manuals explain the internal construction of the CPU, including
the processor registers available and their logical capabilities. They list all hardware-
implemented instructions, specify their binary code format, and provide a precise definition of
each instruction. A computer will usually have a variety of instruction code formats. It is the
function of the control unit within the CPU to interpret each instruction code and provide the
necessary control functions needed to process the instruction.
The format of an instruction is usually depicted in a rectangular box symbolizing the bits
of the instruction as they appear in memory words or in a control register. The bits of the
instruction are divided into groups called fields.
The most common fields found in instruction formats are:

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1 An operation code field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor registers.
3. A mode field that specifies the way the operand or the effective address is
determined.
Q.5 What is ALU?
Ans: An arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic
operations. It represents the fundamental building block of the central processing unit (CPU) of a
computer. Modern CPUs contain very powerful and complex ALUs. In addition to ALUs,
modern CPUs contain a control unit (CU).
Most of the operations of a CPU are performed by one or more ALUs, which load data
from input registers. A register is a small amount of storage available as part of a CPU. The
control unit tells the ALU what operation to perform on that data, and the ALU stores the result
in an output register. The control unit moves the data between these registers, the ALU, and
memory.
Q.6 What Is RAL and RAR ?
Ans: RAL: - Each binary bit of the accumulator is rotated left by one position through the
Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least
significant position D0. CY is modified according to bit D7.
Eg: - RAL
RAR: - Each binary bit of the accumulator is rotated right by one position through the Carry
flag. Bit D0 is placed in the Carry flag, and the Carry flag is placed in the most significant
position D7. CY is modified according to bit D0.
Eg: - RAR
Q.7 What is Bus System In 8085 Microprocessor?
Ans: The microprocessor MPU performs various operations with peripheral devices or a
memory location by using three sets of communication lines called buses: the address
bus, the data bus and the control bus. And these three combined lines is called as system
bus.
Address bus:
The address bus is a group of 16
lines generally called as A0 – A15 to
carry a 16-bit address of memory
location. In a computer system, each
peripheral or memory location is
identified by a binary number called an address. This is similar to the postal address of a
house. The address bus is unidirectional, that means bit flow in only one direction from
MPU to peripheral. MPU carries 16-bit address i.e. 216 = 65,536 or 64K memory
locations.
Data Bus:

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The data bus is a group of eight bidirectional lines used for data flow in both the
directions between MPH and peripheral devices. The 8 data lines are manipulating 8-bit
data ranging from 00 to FF i.e. (28 = 256) numbers from 0000 0000 -1111 1111
This 8 bit data is called as word length and the register size of a microprocessor and MPH
is called 8–bit microprocessor.
Control bus:
Control bus is having various single lines used for sending control signals in the form of
pulse to the memory and I/O devices. The MPU generates specific control signals to
perform a particular operations. Some of these control signals are memory read, memory
write, I/O read and I/O write.
Q.8 What is IOP architecture?
Ans: An input-output processor (IOP) is a processor with direct memory access
capability. In this, the computer system is divided into a memory unit and number of
processors. Each IOP controls and manage the input-output tasks. The IOP is similar to
CPU except that it handles only the details of I/O processing. The IOP can fetch and
execute its own instructions. These IOP instructions are designed to manage I/O transfers
only.
Block Diagram Of IOP
Below is a block diagram of a computer along with various I/O Processors. The memory
unit occupies the central position and can communicate with each processor. The CPU
processes the data required for solving the computational tasks. The IOP provides a path
for transfer of data between peripherals and memory. The CPU assigns the task of
initiating the I/O program. The IOP operates independent from CPU and transfer data
between peripherals and memory.

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Part-II
Q.1 (A) Explain Instruction Cycle in Details.
Ans: Instruction Cycle: The time period during which one instruction is fetched from
memory and executed when a computer is given an instruction in machine language.
There are typically four stages of an instruction cycle that the CPU carries out:
1. Fetch the instruction from memory. This step brings the instruction into the instruction
register, a circuit that holds the instruction so that it can be decoded and executed.
2. Decode the instruction.
3. Read the effective address from memory if the instruction has an indirect address.
4. Execute the instruction.
(B) What is Instruction Timing Diagram and Explain.
Ans: It is one of the best way to understand to process of micro-processor/controller. With the
help of timing diagram we can understand the working of any system, step by step working of
each instruction and its execution, etc.
It is the graphical representation of process in steps with respect to time. The timing
diagram represents the clock cycle and duration, delay, content of address bus and data bus, type
of operation ie. Read/write/status signals.
1. Instruction cycle: this term is defined as the number of steps required by the cpu
to complete the entire process ie. Fetching and execution of one instruction. The fetch and
execute cycles are carried out in synchronization with the clock.
2. Machine cycle: It is the time required by the microprocessor to complete the
operation of accessing the memory devices or I/O devices. In machine cycle various operations
like opcode fetch, memory read, memory write, I/O read, I/O write are performed.
3. T-state: Each clock cycle is called as T-states.
Rules to identify number of machine cycles in an instruction:
1. If an addressing mode is direct, immediate or implicit then No. of machine cycles = No. of
bytes.
2. If the addressing mode is indirect then No. of machine cycles = No. of bytes + 1. Add +1 to
the No. of machine cycles if it is memory read/write operation.

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3. If the operand is 8-bit or 16-bit address then, No. of machine cycles = No. of bytes +1.
4. These rules are applicable to 80% of the instructions of 8085.
Timing Diagram:
Where, Instruction cycle= Fetch Cycle(FC) + Executecycle(EC).
A timing diagram of an instruction is a graphical representation of the time taken by the µP to
fetch, decode and execute an instruction. The size of the instruction and the frequency of the µP
decides the total amount of time taken to execute an instruction. This can be illustrated with the
help of timing diagram. Consider the instruction MVI A, byte. It is basically a two byte
instruction i.e. it requires two memory locations and this instruction can be written as follows:
Memory location Mnemonics Comments Hexcode
2024 MVI A
move immediately
8-bit data in register A
3E
2025 data data
So far as the timing diagram of this instruction is concerned it consists of two machine cycles
M1—opcode fetch and M2—memory read. M1 consists of 4 T-states and M2 consists of 3 T-
states. Figure 4.2 (a) and (b) show the opcode fetch and memory read machine cycles
respectively.

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2.(A) What is DMA ? Explain in Details.
Ans: Direct memory access (DMA) is a method that allows an input/output (I/O) device to send
or receive data directly to or from the main memory, bypassing the CPU to speed up memory
operations. The process is managed by a chip known as a DMA controller (DMAC).
A computer's system resource tools are used for communication between hardware and software.
The four types of system resources are:
 I/O addresses
 Memory addresses
 Interrupt request numbers (IRQ)
 Direct memory access (DMA) channels
DMA channels are used to communicate data between the peripheral device and the system
memory. All four system resources rely on certain lines on a bus. Some lines on the bus are used
for IRQs, some for addresses (the I/O addresses and the memory address) and some for DMA
channels.
A DMA channel enables a device to transfer data without exposing the CPU to a work
overload. Without the DMA channels, the CPU copies every piece of data using a peripheral bus
from the I/O device. Using a peripheral bus occupies the CPU during the read/write process and
does not allow other work to be performed until the operation is completed.
With DMA, the CPU can process other tasks while data transfer is being performed. The
transfer of data is first initiated by the CPU. During the transfer of data between the DMA
channel and I/O device, the CPU performs other tasks. When the data transfer is complete, the
CPU receives an interrupt request from the DMA controller.
DMA Transfer Types
Memory To Memory Transfer
In this mode block of data from one memory address is moved to another memory address.
In this mode current address register of channel 0 is used to point the source address and the
current address register of channel is used to point the destination address in the first transfer
cycle, data byte from the source address is loaded in the temporary register of the DMA
controller and in the next transfer cycle the data from the temporary register is stored in the
memory pointed by destination address. After each data transfer current address registers are
decremented or incremented according to current settings. The channel 1 current word count
register is also decremented by 1 after each data transfer. When the word count of channel 1 goes
to FFFFH, a TC is generated which activates EOP output terminating the DMA service.
Auto initialize
In this mode, during the initialization the base address and word count registers are loaded
simultaneously with the current address and word count registers by the microprocessor. The
address and the count in the base registers remain unchanged throughout the DMA service.
After the first block transfer i.e. after the activation of the EOP signal, the original values of
the current address and current word count registers are automatically restored from the base
address and base word count register of that channel. After auto initialization the channel is
ready to perform another DMA service, without CPU intervention.

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DMA Controller
The controller is integrated into the processor board and manages all DMA data transfers.
Transferring data between system memory and an 110 device requires two steps. Data goes from
the sending device to the DMA controller and then to the receiving device. The microprocessor
gives the DMA controller the location, destination, and amount of data that is to be transferred.
Then the DMA controller transfers the data, allowing the microprocessor to continue with other
processing tasks. When a device needs to use the Micro Channel bus to send or receive data, it
competes with all the other devices that are trying to gain control of the bus. This process is
known as arbitration. The DMA controller does not arbitrate for control of the BUS instead; the
I/O device that is sending or receiving data (the DMA slave) participates in arbitration. It is the
DMA controller, however, that takes control of the bus when the central arbitration control point
grants the DMA slave's request.
2.(B) What the name of Keyboard and Floppy Disk Controller.
Ans: The hex keypad is a peripheral that connects to the DE2 through JP1 or JP2 via a 40-pin
ribbon cable. It has 16 buttons in a 4 by 4 grid, labeled with the hexadecimal digits 0 to F. An
example of this can been seen in Figure 1, below. Internally, the structure of the hex keypad is
very simple. Wires run in vertical columns (we call them C0 to C3) and in horizontal rows
(called R0 to R3). These 8 wires are available externally, and will be connected to the lower 8
bits of the port. Each key on the keypad is essentially a switch that connects a row wire to a
column wire. When a key is pressed, it makes an electrical connection between the row and
column.

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Figure 1: hex keypad layout
Floppy Disk Controller: A floppy disk controller (FDC) is an electronic chip controller used
as an interface between a computer and a floppy disk drive. Modern computers have this chip
embedded in the motherboard, whereas they were a separate component when they were
originally introduced.
A floppy disk controller (FDC) is a specially designed chip that controls the reading and writing
functionality of a floppy drive. An FDC can support up to four floppy disk drives at a time. The
controller is connected to the system bus of the CPU and appears as a set of I/O ports to the
computer. It is usually also linked to a serial bus of the direct memory access (DMA) controller.
In an x86 computer, the floppy disk controller uses IRQ 6, whereas interrupt schemes are used
on other systems. Data transmission is often done by FDC while in DMA mode.
Q.3 (A) Explain Addressing Modes of 8085 Microprocessor.
Ans: Addressing mode refers to the specification of the location of data required by an operation
• Pentium supports three fundamental addressing modes: ∗ Register mode ∗ Immediate mode ∗
Memory mode • Specification of operands located in memory can be done in a variety of ways ∗
Mainly to support high-level language constructs and data structures
The operation field of an instruction specifies the operation to be performed. This
operation must be executed on some data stored in computer registers or memory words. The
way the operands are chosen during program execution in dependent on the addressing mode of
the instruction. The addressing mode of the instruction. The addressing mode specifies a rule for
interpreting or modifying the address field of the instruction before the operand is actually
referenced. Computers use addressing mode techniques for the purpose of accommodating one
or both of the following provisions:
1 To give programming versatility to the user by providing such facilities as pointers to
Memory, counters for loop control, indexing of data, and program relocation
2 To reduce the number of bits in the addressing field of the instruction.
3 The availability of the addressing modes gives the experienced assembly language
programmer flexibility for writing programs that are more efficient with respect to the
number of instructions and execution time.
Although most addressing modes modify the address field of the instruction, there are two
modes that need no address field at all. These are the implied and immediate modes.
1 Implied Mode: In this mode the operands are specified implicitly in the definition of
theinstruction. For example, the instruction ―complement accumulator‖ is an implied-mode
instruction because the operand in the accumulator register is implied in the definition of the
instruction. In fact, all register reference instructions that sue an accumulator are implied-mode
instructions. Figure 1: Instruction format with mode field Zero-address instructions in a stack-
organized computer are implied-mode instructions since the operands are implied to be on top of
the stack.
2 Immediate Mode: In this mode the operand is specified in the instruction itself. Inother
words, an immediate mode instruction has an operand field rather than an address field. The
operand field contains the actual operand to be used in conjunction with the operation specified
in the instruction. Immediate-mode instructions are useful for initializing registers to a constant

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value. It was mentioned previously that the address field of an instruction may specify either a
memory word or a processor register. When the address field specifies a processor register, the
instruction is said to be in the register mode.
3 Register Mode: In this mode the operands are in registers that reside within the CPU.The
particular register is selected from a register field in the instruction. A k-bit field can specify any
one of 2k registers.
4 Register Indirect Mode: In this mode the instruction specifies a register in the CPUwhose
contents give the address of the operand in memory. In other words, the selected register
contains the address of the operand rather than the
5 Auto increment or Auto decrement Mode: This is similar to the register indirect
modeexcept that the register is incremented or decremented after (or before) its value is used to
access memory. When the address stored in the register refers to a table of data in memory, it is
necessary to increment or decrement the register after every access to the table. This can be
achieved by using the increment or decrement instruction. However, because it is such a
common requirement, some computers incorporate a special mode that automatically increments
or decrements the content of the register after data access. The address field of an instruction is
used by the control unit in the CPU to obtain the operand from memory. Sometimes the value
given in the address field is the address of the operand, but sometimes it is just an address from
which the address of the operand is calculated. To differentiate among the various addressing
modes it is necessary to distinguish between the address part of the instruction and the effective
address used by the control when executing the instruction. The effective address is defined to be
the memory address obtained from the computation dictated by the given addressing mode. The
effective address is the address of the operand in a computational-type instruction. It is the
address where control branches in response to a branch-type instruction. We have already
defined two addressing modes in previous chapter.
6 Direct Address Mode: In this mode the effective address is equal to the address part ofthe
instruction. The operand resides in memory and its address is given directly by the address field
of the instruction. In a branch-type instruction the address field specifies the actual branch
address.
7 Indirect Address Mode: In this mode the address field of the instruction gives theaddress
where the effective address is stored in memory. Control fetches the instruction from memory
and uses its address part to access memory again to read the effective address.
8 Relative Address Mode: In this mode the content of the program counter is added to
theaddress part of the instruction in order to obtain the effective address. The address part of the
instruction is usually a signed number (in 2‘s complement representation) which can be either
positive or negative. When this number is added to the content of the program counter, the result
produces an effective address whose position in memory is relative to the address of the next
instruction. To clarify with an example, assume that the program counter contains the number
825 and the address part of the instruction contains the number 24. The instruction at location
825 is read from memory during the fetch phase and the program counter is then incremented by
one to 826 + 24 = 850. This is 24 memory locations forward from the address of the next
instruction. Relative addressing is often used with branch-type instructions when the branch

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address is in the area surrounding the instruction word itself. It results in a shorter address field
in the instruction format since the relative address can be specified with a smaller number of bits
compared to the number of bits required to designate the entire memory address.
9 Indexed Addressing Mode: In this mode the content of an index register is added to the
address part of the instruction to obtain the effective address. The index register is a special CPU
register that contains an index value. The address field of the instruction defines the beginning
address of a data array in memory. Each operand in the array is stored in memory relative to the
beginning address. The distance between the beginning address and the address of the operand is
the index value stores in the index register. Any operand in the array can be accessed with the
same instruction provided that the index register contains the correct index value. The index
register can be incremented to facilitate access to consecutive operands. Note that if an index-
type instruction does not include an address field in its format, the instruction converts to the
register indirect mode of operation. Some computers dedicate one CPU register to function
solely as an index register. This register is involved implicitly when the index-mode instruction
is used. In computers with many processor registers, any one of the CPU registers can contain
the index number. In such a case the register must be specified explicitly in a register field within
the instruction format.
10 Base Register Addressing Mode: In this mode the content of a base register is added to the
address part of the instruction to obtain the effective address. This is similar to the indexed
addressing mode except that the register is now called a base register instead of an index register.
The difference between the two modes is in the way they are used rather than in the way that
they are computed. An index register is assumed to hold an index number that is relative to the
address part of the instruction. A base register is assumed to hold a base address and the address
field of the instruction gives a displacement relative to this base address. The base register
addressing mode is used in computers to facilitate the relocation of programs in memory. When
programs and data are moved from one segment of memory to another, as required in
multiprogramming systems, the address values of the base register requires updating to reflect
the beginning of a new memory segment.
Q.3 (B) Define Vectored interrupt.
Ans: VECTORED INTERRUPT
 In vectored interrupts, the processor automatically branches to the specific address in response
to an interrupt.
 In vectored interrupts, the manufacturer fixes the address of the ISR to which the program
control is to transfer.
 Also, The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts.
 TRAP the only non-mask able interrupt in the 8085.
NON-VECTORED INTERRUPT
 In non-vectored interrupts, the interrupted device should give the address of the interrupt
service routine (ISR).
 Also, The INTR a non-vectored interrupt.
 Hence when a device interrupts through INTR, it has to supply the address of ISR after
receiving interrupt acknowledge signal.

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Software Interrupt
 The software interrupts of 8085 are RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6
and RST 7.
 Also, The software interrupts cannot masked and they cannot be disabled.
Hardware Interrupt
 The vectored hardware interrupts of 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5.
 An external device initiates the hardware interrupts 8O85 by placing an appropriate
signal at the interrupt pin of the processor.
 The processor keeps on checking the interrupt pins at the second T -state of last machine
cycle of every instruction.
 Also, If the processor finds a valid interrupt signal and if the interrupt unmasked and
enabled, then the processor accepts the interrupt.
 The acceptance of the interrupt acknowledged by sending an INTA signal to the
interrupter device.
 Moreover, The processor saves the content of PC (Program Counter) in a stack and then
loads the vector address of the interrupt in PC. (If the interrupt non-vectored, then the
interrupting device has to supply the address of ISR when it receives INTA signal).
 It starts executing ISR at this address.
 At the end of ISR, a return instruction, RET will place.
 Also, When the processor executes the RET instruction, it POP the content on top of the
stack PC.
 Thus the processor control returns to the main program after servicing interrupts.
Q.4. (A) Explain following with example?
a. CMP
b. XRA
c. TNC
d. DAA
e. RIM
f. LXI
g. CMA
h. ADC
Ans: CMP: - (compare register or memory with accumulator) The contents of the operand
register or memory are M compared with the contents of the accumulator. Both contents are
preserved . The result of the comparison is shown by setting the flags of the PSW as follows:
if (A) < reg/mem: carry flag is set.
if (A) = reg/mem:
zero flag is set.
if (A) > reg/mem: carry and zero flags are reset.
XRA: - The content of accumulator are exclusive OR with specified register or memory
location.
Eg: - XRA B
XRA M

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DAA: - Decimal adjust accumulator.
The contents of the accumulator are changed from a binary value to two 4-bit binary coded
decimal (BCD) digits. This is the only instruction that uses the auxiliary flag to perform the
binary to BCD conversion, and the
conversion procedure is described below. S, Z, AC, P, CY flags are altered to reflect the
results of the operation.
If the value of the low-order 4-bits in the accumulator is greater than 9 or if AC flag is set,
the instruction adds 6 to the low-order four bits. If the value of the high-order 4-bits in the
accumulator is greater than 9 or if the Carry flag is set, the instruction adds 6 to the high-
order four bits.
LXI(Load register pair immediate): - The instruction loads 16-bit data in the register pair
designated in the
operand.
Eg: - LXI H, 2034H (2034H is stored in HL pair so that it act as memory pointer)
LXI H, XYZ (address of level XYZ is copied in HL pair)
CMA: - The content of accumulator is complemented.
Eg: - CMA
ADC: Add the data in register Ror memory location M along with the bit in carry flag
with the data in the accumulator and store the result in the accumulator. All flags are
affected.
Eg: ADC R/M

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Q. Explain 8085 Architecture in Details
Ans:
This is the functional block diagram of the 8085 Microprocessor.
This is the function
al Block Diagram of 8085 Microprocessor.
Accumulator:-It is a 8-bit register which is used to perform arithmetical and logical operation. It
stores the output of any operation. It also works as registers for i/o accesses.
Temporary Register:-It is a 8-bit register which is used to hold the data on which the accumulator
is computing operation. It is also called as operand register because it provides operands to ALU.
Registers:-These are general purposes registers. Microprocessor consists 6 general purpose
registers of 8-bit each named as B,C,D,E,H and L. Generally theses registers are not used for
storing the data permanently. It carries the 8-bits data. These are used only during the execution
of the instructions.
These registers can also be used to carry the 16 bits data by making the pair of 2 registers. The

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valid register pairs available are BC,DE HL. We can not use other pairs except BC,DEand HL.
These registers are programmed by user.
ALU:-ALU performs the arithmetic operations and logical operation.
Flag Registers:-It consists of 5 flip flop which changes its status according to the result stored in
an accumulator. It is also known as status registers. It is connected to the ALU.
There are five flip-flops in the flag register are as follows:
1.Sign(S)
2.zero(z)
3.Auxiliary carry(AC)
4.Parity(P)
5.Carry(C)
The bit position of the flip flop in flag register is:
All of the three flip flop set and reset according to the stored result in the accumulator.
1.Sign- If D7 of the result is 1 then sign flag is set otherwise reset. As we know that a number on
the D7 always desides the sign of the number.
if D7 is 1: the number is negative.
if D7 is 0: the number is positive.
2.Zeros(Z)-If the result stored in an accumulator is zero then this flip flop is set otherwise it is
reset.
3.Auxiliary carry(AC)-If any carry goes from D3 to D4 in the output then it is set otherwise it is
reset.

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4.Parity(P)-If the no of 1's is even in the output stored in the accumulator then it is set otherwise
it is reset for the odd.
5.Carry(C)-If the result stored in an accumulator generates a carry in its final output then it is set
otherwise it is reset.
Instruction registers(IR):-It is a 8-bit register. When an instruction is fetched from memory then
it is stored in this register.
Instruction Decoder:- Instruction decoder identifies the instructions. It takes the informations
from instruction register and decodes the instruction to be performed.
Program Counter:-It is a 16 bit register used as memory pointer. It stores the memory address of
the next instruction to be executed. So we can say that this register is used to sequencing the
program. Generally the memory have 16 bit addresses so that it has 16 bit memory.
The program counter is set to 0000H.
Stack Pointer:-It is also a 16 bit register used as memory pointer. It points to the memory
location called stack. Generally stack is a reserved portion of memory where information can be
stores or taken back together.
Timing and Control Unit:-It provides timing and control signal to the microprocessor to perform
the various operation.It has three control signal. It controls all external and internal circuits. It
operates with reference to clock signal.It synchronizes all the data transfers.
There are three control signal:
1.ALE-Airthmetic Latch Enable, It provides control signal to synchronize the components of
microprocessor.
2.RD- This is active low used for reading operation.
3.WR-This is active low used for writing operation.
There are three status signal used in microprocessor S0, S1 and IO/M. It changes its status
according the provided input to these pins.

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Serial Input Output Control-There are two pins in this unit. This unit is used for serial data
communication.
Interrupt Unit-There are 6 interrupt pins in this unit. Generally an external hardware is connected
to these pins. These pins provide interrupt signal sent by external hardware to microprocessor
and microprocessor sends acknowledgement for receiving the interrupt signal. Generally INTA
is used for acknowledgement.
Q 5. Define All Interrupts and Control Pins of 8085 MP.
Ans :

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The 8085 μP is an 8-bit microprocessor capable of addressing 64K of memory. It is a 40-pin IC
which requires a power supply of +5V and it‘s operating frequency is 3MHz. Fig. 3.3 shows the pin
configuration of 8085 μP .The pin configuration of 8085 μP can be classified into six groups namely:
 High order Address bus
 Multiplexed Address/Data bus
Microprocessor 8085 architecture Ace- Pali /CSA/8085 Architecture Assistant Professor: Gajendra
Jingar
 Control and status signals
 Power supply and frequency signals
 Externally initiated signals and
 Serial I/O ports
(1) High order address bus:
The address bus is a group of 16-lines generally identified as A0-A15. The address bus is split into
two segments ADO-AD7 and A 8-A15 .The buses from ADO-AD7 are low order address buses and A8-
A15 buses are high order address buses.
(2) Multiplexed Address/Data bus:
The data bus is a group of 8-lines used for transfer of data. These lines are bidirectional i.e. data
flows in both the directions from μP to peripherals and vice-versa. They are represented as ADO-AD7
because they serve dual purpose. They are used as low-order address bus as well as data bus and
therefore they are known as multiplexed address/data bus.
(3) Control and status signals:
This group of signals includes two control signals, three status signals and one special signal. These
signals are as follows: Control signal: - and ar the two control signals which indicate that the data is
to be read from or written into a selected memory or I/O location. Both are active low signals. Status
signal: - , S1 and SO are the three status signals. is used to differentiate between I/O and memory
operations. When it is high it indicates I/O operation and when it is low it indicates memory
operation. S1 and S O are also status signals but are rarely used in small systems. Special signal: -
ALE (Address Latch Enable) is a special signal used for demultiplexing address and data bus (ADO-
AD7). It is a positive going pulse generated every time a machine cycle begins and so long as it
remains positive it indicates that the bits on ADO-AD7 are address bits.
(4) Power supply and clock frequency:
The power supply required for 8085 μP is +5V. As shown in pinout diagram VCC is connected to
+5V and VSS is connected to the ground of the power supply. The μP operates on frequency of
3MHz, therefore an oscillator of frequency 6MHz is connected between pin no. 1 and 2 as the
frequency is internally divided by two. CLK (OUT) i.e. Pin no. 37 is used as a system clock for other
devices.
(5) Externally initiated signals:
There are certain operations which can be initiated by external devices (or signals). For these
externally initiated operations there are individual pins assigned on the Microprocessor 8085
architecture Ace- Pali /CSA/8085 Architecture Assistant Professor: Gajendra Jingar

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microprocessor chip. Interrupts are also considered as externally initiated signal. Here is a brief
explanation of interrupts and other externally initiated signals. Interrupts: - The 8085 has five
interrupt signals that can be used to interrupt a program execution. These interrupts are
(a) TRAP: The interrupt with highest priority. It is non-maskable and vectored interrupt i.e. the μP
has to attend this interrupt immediately.
(b) RST 7.5, RST 6.5, RST 5.5: These are known as Restart interrupts and have lower priority than
TRAP but have higher priority than the INTR interrupt. They are vectored and maskable interrupts.
Among the three the priority order is RST7.5>RST6.5>RST5.5
(c) INTR: It is a general purpose interrupt. It is maskable and non-vectored interrupt and has the least
priority.
Reset: - When RESET pin is activated, the μP suspends all the internal operations and the program
counter is cleared. Now the program execution can again begin at the zero memory address.
Ready: - The Ready signal is used to synchronize slower peripherals with the microprocessor. If the
signal at READY pin is low the microprocessor enters into a wait state. Hold: - This signal is used
by the external devices to request the microprocessor for using the buses. When this signal is
activated the μP leaves is control over the buses and makes them free for the peripherals to use.
: - Interrupt Acknowledge. This signal is used to acknowledge an interrupt.
HLDA: - Hold Acknowledge. This signal is used to acknowledge the HOLD request.
: - This is an active low signal. When it is activated the buses are restated, the program counter is
cleared and the microprocessor is reset.
RESET OUT: This signal indicates that the microprocessor is being reset. It can be used to reset
other devices also.
(6) Serial I/O Ports:
To send and receive data serially microprocessor has two pins ‗SID‘ and ‗SOD‘ by using these pins
the μP can communicate with other μP and peripheral devices. In serial transmission, data bits are
sent over a single line, one bit at a time. SID is Serial Input Data and SOD stands for Serial Output
Data. SID (Input) – On execution of the RIM instruction the data on this line is loaded into the
seventh bit of the accumulator. SOD(output)- When SIM instruction is executed the 7th bit of the
accumulator is output on SOD line.
Q.6 Write a assembly Program to find Largest in Three numbers.
Ans:
Label Instruction Comments
MVI A, 06H ; Loads Accumulator with 06H
MVI B, 0AH ; Loads register B with 0AH
MVI C, 0BH ; Loads register C with 0BH
CMP B ; Compares B with A
JNC jump1: ; On no carry jumps to jump1:
MOV A, B ; Moves content of B to A
jump1: CMP C ; Compares C with A
JNC jump2: ; On no carry jumps to jump2:
MOV A, C ; Moves content of C to A

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jump2: STA 4200H ; Stores content of A to memory location 4200H
HLT ; Terminates the program
Algorithm Step 1: Load Accumulator (A) with value1
Step 2: Load register B with value2
Step 3: Load register C with value3
Step 4: Compare B with A, gives carry if value2 is greater than value1 (i.e. B>A)
Step 5: When no carry from Step 4: go to Step 7: (i.e. when A>B)
Step 6: Move content of register B to A (i.e. when B>A)
Step 7: Compare C with A, gives carry if value3 is greater than value1 (i.e. C>A)
Step 8: When no carry from Step 7: go to Step10: (i.e. when A>C)
Step 9: Move content of register C to A (i.e. when C>A)
Step 10: Store content of Accumulator to memory location 4200H
Step 11: Terminate the program

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Q. 7 Explain I/O accessing used in Mp.
Ans: Memory-mapped I/O (MMIO) and port-mapped I/O (PMIO) (which is also
called isolated I/O[citation needed]
) are two complementary methods of performing input/output (I/O)
between the central processing unit (CPU) and peripheral devices in a computer. An alternative
approach is using dedicated I/O processors, commonly known as channels on mainframe
computers, which execute their own instructions.
Memory-mapped I/O uses the same address space to address both memory and I/O devices. The
memory and registers of the I/O devices are mapped to (associated with) address values. So
when an address is accessed by the CPU, it may refer to a portion of physical RAM, or it can
instead refer to memory of the I/O device. Thus, the CPU instructions used to access the memory
can also be used for accessing devices. Each I/O device monitors the CPU's address bus and
responds to any CPU access of an address assigned to that device, connecting the data bus to the
desired device's hardware register. To accommodate the I/O devices, areas of the addresses used
by the CPU must be reserved for I/O and must not be available for normal physical memory. The
reservation may be permanent, or temporary (as achieved via bank switching). An example of
the latter is found in the Commodore 64, which uses a form of memory mapping to
cause RAM or I/O hardware to appear in the $D000-$DFFF range.
Port-mapped I/O often uses a special class of CPU instructions designed specifically for
performing I/O, such as the in and out instructions found on microprocessors based on
the x86 and x86-64 architectures. Different forms of these two instructions can copy one, two or
four bytes (outb, outw and outl, respectively) between the EAX register or one of that register's
subdivisions on the CPU and a specified I/O port which is assigned to an I/O device. I/O devices
have a separate address space from general memory, either accomplished by an extra "I/O" pin
on the CPU's physical interface, or an entire bus dedicated to I/O. Because the address space for
I/O is isolated from that for main memory, this is sometimes referred to as isolated I/O.
The characteristics of isolated I/O are as follows:
- The devices of I/O are treated in a separate domain as compared to memory.
- A total of 1mb address space is allowed for memory applications.
- In order to maximize the I/O operations ( isolated ) separate instructions are always provided
to perform these operations.
- One of the disadvantages is that the data transfer only occurs between the I/O port and the
AL, AX registers.
The characteristics of the memory mapped I/O are as follows:
- In such scenarios the devices (I/O) are treated as a part of the memory only.
- Complete 1mb of memory cannot be used as they are a part of the memory.

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- In case of memory mapped I/O operations no external separate instructions are required.
- There is data transfer restriction in case of memory mapped instructions.
Q.8. What is Micro Operation. And Explain.
Ans: Micro operations are classified into four categories: – Register transfer micro operations
(data moves from register to register) – Arithmetic micro operations (perform arithmetic on data
in registers) – Logic micro operations (perform bit manipulation on data in registers) – Shift
micro operations (perform shift on data in registers)
Arithmetic Microoperations
• The RTL statement: R3 ← R1 + R2 indicates an add microoperation. We can similarly specify
the other arithmetic microoperations.
• Multiplication and division are not considered microoperations.
– Multiplication is implemented by a sequence of adds and shifts.
– Division is implemented by a sequence of substracts and shifts.
Arithmetic Microoperations
Example Description
R3 ← R1 + R2 Addition
R3 ← R1 - R2 (R1 + R2' + 1) Subtraction
R2 ← R2' Complement (really a logic operation)
R2 ← -R2 (R2' + 1) Negation
R1 ← R1 + 1 Increment
R1 ← R1 - 1 Decrement
Increment and decrement can be done with combinational incrementers and decrementers,
counter registers, or by adding a 1. ( Where does the 1 come from? ) Multiply and divide are not
often implemented as microoperations due to the amount of time they require. They are usually
implemented as a multi-clock-cycle routine of shifts and adds.
Logic Microoperations
Logic operations are performed independently on all bits of a word.
10100010
^ 01001010
------------
00000010
As a result, the logic circuit is simply a group of gates working independently on each bit.
To implement a single circuit with many logic functions, simply use a multiplexer.
One bit stage of a logic circuit with 4 functions.
Logic operations are used heavily in systems programming (device drivers, etc.), cryptography,
etc.
 Selective set
 Selective complement

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 Selective clear
specify binary operations on the strings of bits in registers.
- useful for bit manipulations on binary data
AND: Mask out certain group of bits
OR : Merge binary or character data
- useful for making logical decisions based on the bit value
Applications Manipulating individual bits or a field(portion) of a word in a register
- Selective-set A + B
- Selective-complement A ⊕ B
- Selective-clear A • B
- Mask (Delete) A • B
- Insert (A • B) + C
- Compare A ⊕ B
- Packing (A • B) + C
- Unpacking A • B
A logical shift operation transfers 0 through the serial input. We use the symbols shl and shr for
logical
shift left and shift right micro operations, e.g.

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R1 ¬ shl R1
R2 ¬ shr R2
are the two micro operations that specify a 1-bit shift left of the content of register R1 and a 1-
bit shift right
of the content of register R2.
The circular shift is also known as rotate operation. It circulates the bits of the register around
the two ends and there is no loss of information. This is accomplished by connecting the serial
output of the shift register to its serial input. We use the symbols cil and cir for the circular shift
left and circular shift right. E.g.
suppose Q1 register contains 01101101 then after cir operation, it contains 0110110 and after cil
operation
it will contain 11011010.
An arithmetic shift micro operation shifts a signed binary number to the left or right. The effect
of an arithmetic shift left operation is to multiply the binary number by 2. Similarly an arithmetic
shift right divides the number by 2. Because the sign of the number must remain the same
arithmetic shift-right must leave the sign bit unchanged, when it is multiplied or divided by 2.
The left most bit in a register holds the sign bit, and the remaining bits hold the number. The sign
bit is 0 for positive and 1 for negative. Negative numbers are in 2‘s complement form. Following
figure shows a typical register of n bits.
Rn-1 Rn-2 ® R1 R0
Sign bit Arithmetic shift right
Bit Rn-1 in the left most position holds the sign bit. Rn-2 is the most significant bit of the
number and R0 is
the least significant bit. The arithmetic shift-right leaves the sign bit unchanged and shifts the
number
(including the sign bits) to the right. Thus Rn-1 remains the same, Rn-2 receives the bit from Rn-
1, and so on

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