1. OMKAR REVANKAR
7825 McCallum Blvd, apt 515, Dallas, TX-75252.
omi4everarsenal@gmail.com | 469-974-4659 | omkarrevankar |
EDUCATION
The University of Texas at Dallas Aug. 2018 – Aug. 2020
M.S in Electrical Engineering (Digital Systems) GPA- 3.3/4.0
Terna Engineering College (University of Mumbai) Sept 2012 – Aug. 2016
B.E. in Electronics Engineering GPA-7.85/10
TECHNICAL SKILLS
EDA Tools: Xilinx ISE Design suite, Aldec Riviera Pro, Modelsim, Cadence Virtuoso, Synopsys VCS, Synopsys
Design Vision, Synopsys SiliconSmart, PrimeTime, Encounter, Synopsys Tetramax, Hspice.
Languages: Verilog HDL (proficient), System Verilog HVL (proficient), Perl scripting (intermediate), Python scripting
(beginner), C and JAVA (beginner).
Certification: Maven Silicon certified Advanced VLSI Design and Verification.
Courses: Analog IC design, Advanced Digital Logic, VLSI Design, Wireless Sensor Network, Computer Architecture,
Microprocessor System Network.
WORK EXPERIENCE
Intern, Maven Silicon Pvt Ltd, Bangalore Jan 2017 – Aug. 2017
Router 1X3- design and verification Feb 2017– Mar 2017
EDA Tools: Xilinx-ISE, Aldec Riviera-Pro Language: Verilog HDL, System Verilog HVL
Designed, synthesized and verified the source code in UVM (universal verification methodology) environment.
The test cases included different size payload, FIFO full condition, packet which is never read, corrupt
packet, simultaneous read and write operation.
AHP to APB Bridge IP core verification May 2017–June 2017
EDA Tools: Aldec Riviera-Pro Language: System Verilog HVL
Architected the class-based verification environment in UVM. (universal verification methodology). Verified the
RTL with single master and single slave for test cases which included different wrap and increment bursts.
Generated functional and code coverage for the RTL verification sign-off.
AMBA-AXI protocol verification June 2017 – July 2017
EDA Tools: Aldec Riviera-Pro Language: System Verilog HVL
Architected the class-based verification environment in UVM (universal verification methodology).
Verified the AMBA-AXI protocol with single master and single slave and five different interfaces for
respective channels for test cases which included simultaneous read and write operations with different
fixed, increment and wrap bursts.
Ethernet Sublayer Design July 2017–Aug 2017
EDA Tools: Xilinx-ISE Language: Verilog HDL
Designed the Reconciliation Sublayer (RS), Physical Coding Sublayer (PCS) and Physical Medium Attachment
(PMA) layer of the data link and physical layer of OSI model. IEEE 8b/10b encoding and decoding standard were
used to transmit code-groups between the receiver and transmitter block.
PROJECTS
16-bit ALU with 16X16 Synchronous RAM Aug 2018 – Dec 2018
Implemented a Behavioural Verilog module of a 16-bit ALU with 16X16 Synchronous RAM by using Xilinx ISE.
Synthesized the module and generated a mapped Verilog netlist using Design vision. Designed a standard
cell library of 8 cells. Ran DRC, LVS, QRC and performed HSPICE simulation and verified their functionality
and delays. Performed library characterization of all the cells using Silicon Smart. Worst case delay from
Static Timing Analysis using PrimeTime. Encounter (Automatic Placement and Routing tool from Cadence)
was used for final sign off.
2. Two stage amplifier design Jan 2019 – May 2019
Designed a differential-input single-ended output Two stage amplifier using 0.35um CMOS technology. The amplifier
is modelled so as to meet the given specifications and keep the system stable. The amplifier design and simulation
were done using Cadence and Hspice.
ADDITIONAL INFORMATION
Personal Skills: Creative and Logical, Leadership qualities, organizing capabilities, Goal attainment, Quick Learner,
Problem solving ability, Innovative, Strategic Thinking, Co-operative and a Keen observer.
Languages: Proficient- English, Hindi, Marathi.
Eligibility: Authorized to work in the United States without sponsorship till 2023 on F1 visa as a part of OPT/ CPT.
