1. Mohamed Abubacker Anwargani
9855 Valley Ranch Pkwy W Apt 2065 • Irving, TX 75063 • (210)913-5913 • abu9022@gmail.com
OBJECTIVE
Seeking to obtain ASIC Design/ASIC Verification Engineer position that will utilize my skills to
develop and verify chips to given specification.
EDUCATION
University of Texas at San Antonio San Antonio, TX
MS, Electrical Engineering. GPA: 3.04/4.00 December ‘14
Relevant Coursework: VLSI system design, FPGA and HDL
Anna University Chennai, India
Relevant Coursework: Digital Electronics, Computer Architecture May ‘11
EXPERIENCE
University of Texas at San Antonio San Antonio, TX
New timing error detecting sequential design January ‘14 – November ‘14
 Examined Razor Logic, where flip flop fail to capture the late signal, the latch capture it, and
the XOR gate send out an error signal
 Applied Perl script matching technique to redesign Razor Logic to Two phase latch-based
design in short interval of time, which helps to find timing error detection
 Run logic simulation by Synopsys VCS with the SDF file for LEON2 processor, to detect all
timing errors
University of Texas at San Antonio San Antonio, TX
Hardware Implementation of Triple DES Algorithm August ’12-December ‘12
 Worked on Triple DES, which involved cascading of encryption and decryption process circuit
block inside a single chip
 Simulated Triple DES code written in Verilog RTL, by using Xilinx ISE simulator and later
used in Cadence SOC Encounter from RTL to GDS-2 design flow to implement Algorithm in
Hardware
 Finally, it produces the best optimized low power chip with area ~1334033 µm2
and total power
dissipation is ~58.87 µW
Leadership and Activities
Getting Excited about Robotics San Antonio, TX
Judge October ‘13
 Inspired students to pursue STEM related career by conducting robotic competition for middle
and high school students
 Distributed prizes based on category such as best themed, pinnacle award and most elegant
robots
SKILLS AND INTERESTS
Technical: Expert in C, Perl, Verilog; Frequent user of UNIX; Basics of C++, System Verilog
Tools: Cadence SOC Encounter, Synopsys Design Compiler, Synopsys PrimeTime