PCI is a hardware bus used for adding internal components to a desktop computer.

1. PCI vs PCI-X vs PCIe
G.Sunodh Kumar
Design Verification Enginner

2. History of PCI

3. History
 The first real high-speed slot to be released was the VLB. The higher speed
was achieved by tying the slot to the CPU local bus, i.e., the CPU external
bus.
 The first industry-wide solution appeared in 1992, when Intel lead the
industry to create “the definitive” expansion slot.Later, other companies
joined the alliance, which is known today as PCI-SIG (PCI Special Interest
Group). The PCI-SIG is responsible for standardizing the PCI, PCI-X and
PCI Express slots.Even though these names are similar, they refer to
completely different technologies.

4. History: The most common types of expansion slots that were launched for the PC
throughout its history
Bus Type Bus Width Bus Speed Bus Bandwidth
ISA - Industry Standard
Architecture
8/16 8.33 MHZ 8 MB/S | 16 MB/S
MCA - Micro Channel
Architecture
16/32 5 MHZ 10 MB/S | 20 MB/S
EISA - Extended Industry
Standard Architure
32 8.33 MHZ 33 MB/S
VESA Local Bus - Video
Electronics Standards Associations
32 25 - 40 MHZ 128 - 132 MB/S
PCI v1.0 - Peripheral
Component Interconnect
32 33 MHZ 133 MB/S
PCI v2.0 64 33 MHZ 264 MB/S
PCI X (Extended) v1.0 64 66 MHZ 512 MB/S
AGP - Accelerated Graphics
Ports
32 66 MHZ 266 - 2133 MB/S
PCI X v2.0 64 266 MHZ & 533 MHZ 2132 MB/S & 4266 MB/S

5. PCIe - Peripheral Component Interconnect Express
Below are Versions of PCIe
Bus Type Encoding Bus(Clk) Speed Bus Bandwidth
PCIe v1.0 8b/10b 2.5 GHZ 250 MB/S(x1 link)
PCIe v2.0 8b/10b 5 GHZ 500 MB/S(x1 link)
PCIe v3.0 128b/130b 8 GHZ 1 GB/S(x1 link)
PCIe v4.0 128b/130b 16 GHZ 2 GB/S(x1 link)
PCIe v5.0 128b/130b 32 GHZ 4 GB/S(x1 link)

6. PCI vs PCI-X vs PCIe

7. Difference between PCI,PCI-X,PCIe
 PCI - Peripheral Component Interconnect
 The PCI is a platform-independent bus that is connected to the system using
a bridge chip (which is part of the motherboard chipset). Whenever a new
CPU is released, you can still use the same PCI bus by redesigning the
bridge chip instead of redesigning the bus, which was the norm before the
PCI bus was created.
 On a motherboard using standard PCI slots, all PCI devices are connected to
the PCI bus and share the same data path, so a bottleneck (i.e., performance
decrease because more than one device wants to transmit data at the same
time) may occur.

8. Difference between PCI, PCI-X, PCIe
 PCI - X (Peripheral Component Interconnect eXtended)
 The PCI-X bus is a version of the PCI bus working at higher clock rates
and with wider data paths for server motherboards.
 To achieve higher speeds without changing the PCI signaling model,
PCI‐X PLL (phase‐locked loop) clock generators that provide
phase‐shifted clocks internally. That allows the outputs to be driven a
little earlier and the inputs to be sampled a little later( latching,resulting
shorter setup time), improving the timing on the bus & increased the
time available for signal propagation on the bus and allowed higher
clock frequencies.

9. Difference between PCI, PCI-X, PCIe
 PCI - X (Peripheral Component Interconnect eXtended)

10. Difference between PCI, PCI-X, PCIe
 PCIe - Peripheral Component Interconnect Express
 The PCI-SIG developed a connection called PCI Express (formerly
known as “3GIO” ,PCI Express works radically different from the
PCI bus.
 PCI is a bus, whereas PCI Express is a point-to-point connection,
i.e., it connects only two devices; no other device can share this
connection.
 On a motherboard with PCI Express slots, each PCI Express slot
is connected to the motherboard chipset using a dedicated lane,
not sharing this lane (data path) with other PCI Express slots.

11. Difference between PCI, PCI-X, PCIe

12. PCI vs PCIe - Communication Technology (Parallel to Serial)
 Before the PCI Express, all PC buses and expansion slots used parallel
communication.
 In parallel communication several bits are transferred on the data path at the
same time.
 In serial communication, only one bit is transferred on the data path per clock
cycle.
 Parallel communication, though, suffers from some issues the higher the
clock, the greater will be the problems with electromagnetic interference
(EMI) and propagation delay.

13. PCI vs PCIe - From Parallel to Serial
 Each bit in parallel communication is transmitted on a separate wire,
data transmitted through shorter wires arrive before the data that are
transmitted through longer wires.
 This cause propagation delay and becomes worse with the increase
in the clock rates.
 On a typical serial communication, four wires are necessary – two
for transmitting data and two for receiving.

14. PCI vs PCIe - From Parallel to Serial
 Usually with a technique against electromagnetic interference called
“cancellation or differential transmission”.
 With the cancellation, the same signal is transmitted on two wires, with the
second wire transmitting the signal “mirrored” (inverted polarity) compared to
the original signal.
 When the receiver gets the signal, it can compare the two signals, which must
be equal but “mirrored.” The difference between the two signals is noise,
making it very simple for the receiver to know what noise is and to discard it.

15. Difference between Parallel to Serial communication
 Parallel communication is usually half-duplex (the same wires are used to
transmit and to receive data) due to the high number of wires that are
necessary for its implementation.
 With a half-duplex communication, two devices can’t talk to each other at
the same time; either one or the other is transmitting data.
 Serial communication is full-duplex (there is a separate set of wires to
transmit data and another set of wires to receive data) because it needs just
two wires each way.
 With full-duplex communication, both devices can be transmitting data at
the same time.

16. “Isn’t serial communication slower ?”
 It depends on what you are comparing.
 If you compare a parallel communication of 33 MHz transmitting 32 bits per
clock cycle, it will be 32 times faster than a serial communication of 33 MHz
transmitting only one bit at a time.
 However, if you compare the same parallel communication to a serial
communication working at a much higher clock rate, the serial communication
may be, in fact, much faster. Just compare the bandwidth of the original PCI
bus, which is 133 MB/s (33 MHz x 32 bits), with the lowest bandwidth you
can achieve with a PCI Express connection (250 MB/s, 2.5 GHz x 1 bit).

17. PCI Bus
Architecture Overview

18.  PCI uses three models for data transfer just as previous bus models did:
Programmed I/O (PIO), DMA and Peer‐to‐peer.
PCI Bus Architecture Perspective
a
 PCI Transaction Models

19.  PIO was commonly used in the early days of the PC because designers were
reluctant to add the expense or complexity to their devices of transaction
management logic. The processor could do the job faster than any other device
any‐way so, in this model, it handles all the work.
 For example, if a PCI device interrupts the CPU to indicate that it needs to put
data in memory, the CPU will end up reading data from the PCI device into an
internal register and then copying that register to memory.
 The process works but is inefficient for two reasons. First, there are two bus
cycles generated by the CPU for every data transfer, and second, the CPU is
busy with data transfer housekeeping rather than more interesting work.
PCI Bus Architecture Perspective
a
 Programmed I/O

20.  In this model another device, called a DMA engine, handles the details of memory
transfers to a peripheral on behalf of the processor.
 Once the CPU has programmed the starting address and byte count into it, the DMA
engine handled the bus protocol and address sequencing on its own. This didn’t
involve any change to the PCI peripherals and allowed them to keep their low‐cost
designs. Later, improved integration allowed peripherals to integrate this DMA
functionality locally, so they didn’t need an external DMA engine. These devices
were capable of handling their own bus transfers and were called Bus Master
devices.
 The DMA method of data transfer is more efficient because the CPU is not involved
in the data movement, and a single bus cycle may be sufficient to move a block of
data.
PCI Bus Architecture Perspective
a
 Direct Memory Access (DMA)

21.  PCI Bus Master could initiate a transfer to another PCI device, with the result that the
entire transaction remains local to the PCI bus and doesn’t involve any other system
resources. Since this transaction takes place between devices that are considered peers
in the system, it’s referred to as a peer‐to‐peer transaction.
 This has some obvious efficiencies because the rest of the system remains free to do
other work. Nevertheless, it’s rarely used in practice because the initiator and target
don’t often use the same format for the data unless both are made by the same vendor.
Consequently, the data usually must first be sent to memory where the CPU can
reformat it before it is then transferred to the target, defeating the goal of a peer‐to‐peer
transfer.Since PCI devices today are almost all capable of being bus‐master, they are
able to do both DMA and peer‐to‐peer transfers.
PCI Bus Architecture Perspective
a
 Peer to Peer

22. Basics of PCI Based System
 PCI connects the CPU with some things that are attached to a PC via the PCI: graphic
card, memory, USB controllers, SATA controllers.
 BDF (or B/D/F) stands for Bus, Device, Function.
 The PCI specification permits a system to host up to 256 buses. (8 bits)
 Each bus can have up to 32 devices. (5 bits)
 Each device can have up to 8 functions. (3 bits)
 Each function of device is idetified by 16 bit address(bus_addrs,device,function)
 Every PCI device has a unique vendor and device ID, device number distinguishes
between PCI devices with the same vendor and device ID.

23. Basics of PCI Based System
 The system includes a North Bridge (called “north” because if the diagram is
viewed as a map, it appears geographically north of the central PCI bus) that
interfaces between the processor and the PCI bus. Associated with the North
Bridge is the processor bus, system memory bus, AGP graphics bus, and PCI.
Several devices share the PCI bus and are either connected directly to the bus
or plugged into an add‐in card connector.
 A South Bridge connects PCI to system peripherals, such as the ISA bus
where legacy peripherals were carried forward for a few years. The South
Bridge was typically also the central resource for PCI that pro‐ vided system
signals like reset, reference clock, and error reporting.

24. Basics of PCI

25. Why PCI to PCI Bridge ?
 Due to some practical electrical limit PCI support only10 to 12 electrical loads
at the base frequency of 33MHz.
 To connect more loads in a system,the solution was to move PCI out of the
main path between system peripherals and memory and replacing the chipset
interconnect PCI‐to‐PCI bridge
 A PCI Bridge is an extension to the topology. Each Bridge creates a new PCI
bus that is electrically isolated from the bus above it, allowing another 10‐12
loads. Some of these devices could also be bridges, allowing a large number
of devices to be connected in a system. The PCI architecture allows up to 256
buses in a single system and each of those buses can have up to 32 devices.

26. Basics of PCI - Topology

27. PCI Bus Transactions
 Every function is capable of acting as a target for transactions on the bus, and
most will also be able to initiate transactions. Such an initiator (called a Bus
Master) has a pair of pins (REQ# and GNT#) dedicated to arbitrating for use
of the shared PCI bus.
 Request (REQ#) pin indicates that the master needs to use the bus and is sent
to the bus arbiter for evaluation against all the other requests at that moment.
 The arbiter decides which requester should be the next owner of the bus and
asserts the Grant (GNT#) pin for that device.
 PCI Initiator & Target

28. PCI Bus Transactions - Arbitration

29. Data Transfer Signal on PCI Bus
Name Function
CLK A 33-MHz or 66MHz clock
FRAME# Sent by the initiator to indicate the duration of a
transaction
AD 32 address/data lines, which may be optionally
increased to 64
C/BE# 4 command/byte-enable lines (8 for 64-bit bus)
IRDY#,
TRDY#
Initiator-ready and Target-ready signals
DEVSEL# A response from the device indicating that it has
recognized its Address and is ready for a data
transfer transaction
IDSEL# Initialization Device Select

30. PCI architecture supports 3 address spaces
32 bit & 64 bit Memory address mapping
I/O mapping
Configuration address space
PCI Bus Address Space Mapping

31. Thank You