This ppt is about pipelining.

1. PIPELINING

2. North Western University, Khulna
Department of Computer Science & Engineering
Course Title: Parallel and Distributed Processing
Course Code: CSE-4105
Submitted To:
Sajib Chatterjee
Lecturer
Dept. of CSE
North Western University, Khulna

3. Pipelining: It is an implementation technique where
multiple instructions are overlapped in execution. The
computer pipeline is divided in stages. Each stage
completes a part of an instruction in parallel. Instead, it
increases instruction throughput.
PIPELINING

4. Each stage completes a part of an instruction in parallel. The stages are connected one to the next
to form a pipe - instructions enter at one end, progress through the stages, and exit at the other
end. Pipelining does not decrease the time for individual instruction execution.
HOW PIPELINE WORKS?

5. PIPELINED VS NON-PIPELINED CASE

6. TIMING DIAGRAM FOR INSTRUCTION PIPELINE OPERATION

7. A cache memory is basically developed to increase the efficiency of the system and to maximize
the utilization of the entire computational speed of the processor.
ROLE OF CACHE MEMORY IN PIPELINING

8. PIPELINE HAZARD
Hazard
Instruction Hazard
Structural Hazard
Data Hazard

9. Data hazard: Any condition in which either the source
or the destination operands of an instruction are not
available at the time expected in the pipeline.
DATA HAZARD

10. Structural hazard: The situation when two instructions
require the use of a given hardware resource at the
same time.
STRUCTURAL HAZARD

11. Instruction (control) hazard: A delay in the availability of
an instruction causes the pipeline to stall.
INSTRUCTION HAZARD

12. Instruction throughput increases.
Increase in the number of pipeline stages increases the number of instructions executed
simultaneously.
Faster ALU can be designed when pipelining is used.
Pipelined CPU’s works at higher clock frequencies than the RAM.
Pipelining increases the overall performance of the CPU.
ADVANTAGES OF PIPELINING

13. Designing of the pipelined processor is complex.
Instruction latency increases in pipelined processors.
The throughput of a pipelined processor is difficult to predict.
The longer the pipeline, worse the problem of hazard for branch instructions.
DISADVANTAGES OF PIPELINING

14. Prepared by:
Name: Jannatun Tuba Jyoti
ID: 20173013010

15. Thank You!!