Recommended
More Related Content
What's hot
What's hot (20)
Similar to Latch & Flip-Flop.pptx
Similar to Latch & Flip-Flop.pptx (20)
More from GargiKhanna1
Recently uploaded
Recently uploaded (20)
Latch & Flip-Flop.pptx
- 1. Latch & Flip-Flop By: Dr. Gargi Khanna Assoc. Prof. ECE Deptt. NIT Hamirpur
- 2. Latch • Latch Function – store a data value • non-volatile; will not lose value over time • –often incorporated in static memory • building block for a master-slave flip flop Static CMOS Digital Latch • most common structure • •cross-coupled inverters, in positive feedback arrangement • circuit forces itself to maintain data value • inverter a outputs a 1 causing inverter b to output a 0 • or, inverter a outputs a 0 causing inverter b to output a 1
- 3. D Latch • When CLK = 1, latch is transparent • – D flows through to Q like a buffer • When CLK = 0, the latch is opaque • – Q holds its old value independent of D • Transparent latch or level-sensitive latch
- 4. D-Latch
- 5. Dynamic D Latch Circuits
- 6. Sequential Logic Slide 6 Latch Design • Pass Transistor Latch • Pros + + • Cons • • • • • • D Q
- 7. Sequential Logic Slide 7 Latch Design • Pass Transistor Latch • Pros + Tiny + Low clock load • Cons • Vt drop • nonrestoring • backdriving • output noise sensitivity • dynamic • diffusion input D Q Used in 1970’s
- 8. Sequential Logic Slide 8 Latch Design • Transmission gate + - D Q
- 9. Sequential Logic Slide 9 Latch Design • Transmission gate + No Vt drop - Requires inverted clock D Q
- 10. Sequential Logic Slide 10 Latch Design • Inverting buffer + + + Fixes either • • • D X Q D Q
- 11. Sequential Logic Slide 11 Latch Design • Inverting buffer + Restoring + No backdriving + Fixes either • Output noise sensitivity • Or diffusion input • Inverted output D X Q D Q
- 12. Static D Latch Design
- 14. Sequential Logic Slide 14 Latch Design • Tristate feedback + • Q D X
- 15. Static D Latch
- 16. Sequential Logic Slide 16 Latch Design • Tristate feedback + Static • Backdriving risk • Static latches are now essential Q D X
- 17. Sequential Logic Slide 17 Latch Design • Buffered input + + Q D X
- 18. Sequential Logic Slide 18 Latch Design • Buffered input + Fixes diffusion input + Noninverting Q D X
- 19. Sequential Logic Slide 19 Latch Design • Buffered output + Q D X
- 20. Sequential Logic Slide 20 Latch Design • Buffered output + No backdriving • Widely used in standard cells + Very robust (most important) - Rather large - Rather slow (1.5 – 2 FO4 delays) - High clock loading Q D X
- 21. Sequential Logic Slide 21 Latch Design • Datapath latch + - Q D X
- 22. Sequential Logic Slide 22 Latch Design • Datapath latch + Smaller, faster - unbuffered input Q D X
- 24. Sequential Logic Slide 24 Flip-Flop Design • Flip-flop is built as pair of back-to-back latches D Q X D X Q Q
- 25. D Flip Flop Master-Slave Concept – cascade 2 latches clocked on opposite clock phases • φ = 1, φ = 0: D passes to master, slave holds previous value • φ = 0, φ = 1 : D is blocked from master, master holds value and passes value to slave Triggering – Output only changes on clock edge; output is held when clock is at a level value (0 or 1) – Positive Edge • output changes only on rising edge of clock – Negative Edge • output changes only on falling edge of clock
- 26. D Flip Flop • Transmission Gate as switch
- 27. D F/F Operation
- 28. Sequential Logic Slide 28 Enable • Enable: ignore clock when en = 0 • Mux: increase latch D-Q delay • Clock Gating: increase en setup time, skew D Q Latch D Q en en Latch D Q 0 1 en Latch D Q en D Q 0 1 en D Q en Flop Flop Flop Symbol Multiplexer Design Clock Gating Design
- 29. Sequential Logic Slide 29 Reset • Force output low when reset asserted • Synchronous vs. asynchronous D Q Q reset D Q D reset Q D reset reset reset Synchronous Reset Asynchronous Reset Symbol Flop D Q Latch D Q reset reset Q reset
- 30. Sequential Logic Slide 30 Set / Reset • Set forces output high when enabled • Flip-flop with asynchronous set and reset D Q reset set reset set
- 31. D Flip Flop with Set/Clear
- 32. Transmission Gate D F/F
- 34. The inputs of the RS latch are precharged and selectively discharged at the rising edge of the clock signal. The RS latch retains the data output during the precharge period when CLK is low. The transistor M 5 provides a current path to ground if the input switches after the rising edge of the clock. This prevents the sources of M 2 and M 4 to become floating, which can cause the inputs of the RS latch to have an intermediate voltage level.
- 35. Complementary Clock CMOS C2CMOS F/F
- 36. Precharge True Single Phase Clock F/F
- 37. Non Precharge TSPC F/F
- 38. Precharge Cascode Voltage Switch Logic F/F
- 41. Power dissipation of self-gating flip-flop and regular flip-flop.
- 42. Double edge triggered flip-flop.
- 43. Power consumption of SETFF and DETFF
Editor's Notes
- This circuit was reportedly used in a RISC microprocessor [4.14]. The flip-flop contains a simple differential feedback circuit that drives an RS latch. The transistors M I' M 2' M 3' M 4 form a pair of cross coupled feedback inverters. The inputs of the RS latch are precharged and selectively discharged at the rising edge of the clock signal. The RS latch retains the data output during the precharge period when CLK is low. The transistor M 5 provides a current path to ground if the input switches after the rising edge of the clock. This prevents the sources of M 2 and M 4 to become floating, which can cause the inputs of the RS latch to have an intermediate voltage level. Although only three transistors are connected to the single phase clock signal, one of the nodes at the inputs of the RS latch is always charged and discharged during evaluation. Note that the full CMOS implementation does not consume static current when the clock is stopped.