Design of Synchronous and Asynchronous Counter

1. COUNTERS
BY‫׃‬
GARGI KHANNA
ECE DEPTT., NIT HAMIRPUR

2. FLIP-FLOP APPLICATIONS
• Applications of Flip-Flop:-
• Counters
• Asynchronous Counter
• Synchronous Counter
• Register
2

3. COUNTERS
• A counter is a register that goes through a predetermined
sequence of states upon the application of clock pulses.
• Asynchronous counters
• Synchronous counters
• Async. counters (or ripple counters)
• the clock signal (CLK) is only used to clock the first FF.
• Each FF (except the first FF) is clocked by the preceding FF.
• Sync. counters,
• the clock signal (CLK) is applied to all FF, which means that all FF
shares the same clock signal,
• thus the output will change at the same time.
3

4. ASYNCHRONOUS COUNTERS
• Modulus (MOD) – the number of states it counts in a complete cycle before it goes
back to the initial state.
• Thus, the number of flip-flops used depends on the MOD of the counter (ie; MOD-4
use 2 FF (2-bit), MOD-8 use 3 FF (3-bit), etc..)
• Example: MOD-4 ripple/asynchronous up-counter.
4

5. ASYNCHRONOUS COUNTERS (CONTINUE)
• The asynchronous counter that counts 4 number starts from 00→01→10→11 and
back to 00 is called MOD-4 ripple (asynchronous) up-counter.
• Next state table and state diagram
5
Present State Next State
Q1Q0 Q1Q0
00 01
01 10
10 11
11 00
00
01
10
11

6. ASYNCHRONOUS COUNTERS (CONTINUE)
• MOD-4 Asynchronous up-counter
6
J Q
K Q
CLK
1 J Q
K Q
CLK
1
Q0 (LSB) Q1 (MSB)
CLK
Q1 0 0 1 1 0 0 1 1 0
Q0 0 1 0 1 0 1 0 1 0
Binary 0 → 1 → 2 → 3 → 0 → 1 → 2 → 3 → 0
CLK

7. ASYNCHRONOUS COUNTERS (CONTINUE)
• MOD-8 Asynchronous up-counter
7
J Q
K Q
CLK
1 J Q
K Q
CLK
1 J Q
K Q
CLK
1
C B A
A 0
B 0
C 0
CLK

8. ASYNCHRONOUS COUNTERS (CONTINUE)
• Next state table and state diagram
8
Present State Next State
ABC ABC
000 001
001 010
010 011
011 100
100 101
101 110
110 111
111 000
0
1
2
3
7
6
5
4

9. ASYNCHRONOUS COUNTERS (CONTINUE)
• 2-bit Asynchronous down counter
9
J Q
K Q
CLK
1 J Q
K Q
CLK
1
B (LSB) A (MSB)
CLK
B 0 1 0 1 0 1 0 1 0
A 0 1 1 0 0 1 1 0 0
Binary 0 → 3 → 2 → 1 → 0 → 3 → 2 → 1 → 0
CLK

10. ASYNCHRONOUS COUNTERS (CONTINUE)
• So far, we have design the counters with MOD number equal to
2N, where N is the number of bit (N = 1,2,3,4….) (also
correspond to number of FF)
• Thus, the counters are limited on for counting MOD-2, MOD4,
MOD-8, MOD-16 etc..
• The question is how to design a MOD-5, MOD-6, MOD-7,
MOD-9 which is not a MOD-2N (MOD  2N) ?
• MOD-6 counters will count from 010 (0002) to 510(1012) and
after that will recount back to 010 (0002) continuously.
10

11. ASYNCHRONOUS COUNTERS
• MOD-6 ripple up-counter (MOD  2N)
11
Present St. Next St.
ABC ABC
000 001
001 010
010 011
011 100
100 101
101 000(110)
0
1
2
3
5
4
Reset the state to 0002
when 1102 is detected

12. ASYNCHRONOUS COUNTERS (CONTINUE)
• Circuit diagram for MOD-6 ripple up-counter (MOD  2N)
12
J Q
K
CLR
Q
CLK
1 1 1
C B A
J Q
K
CLR
Q
CLK
J Q
K
CLR
Q
CLK
Detect the output at
ABC=110 to activate
CLR. NAND gate is used
to detect outputs that generates ‘1’!
CLK

13. MOD-4 ASYNCHRONOUS COUNTER
D FLIP FLOP
13

14. CHIP FOR ASYNCHRONOUS COUNTERS
• 74293 IC for Asynchronous counter with Reset (MR1 and MR2)
14
MR1
MR2
Q0
Q1
Q2
Q3 CP0
CP1
74293
J Q
K
CLR
Q
CLK
1 1 1
Q0 Q1 Q2
J Q
K
CLR
Q
CLK
J Q
K
CLR
Q
CLK
1 J Q
K
CLR
Q
CLK
Q3
MR1
MR2
CP0
CP1

15. CHIP FOR ASYNCHRONOUS
COUNTERS (CONTINUE)
• Using 74293 IC to design MOD  16 asynchronous up-
counter!
• Exercise:
• use 74293 IC to design MOD-10 ripple up-counter
15
MR1
MR2
Q0
Q1
Q2
Q3
CP0
CP1
74293
1 0 1 0

16. CHIP FOR ASYNCHRONOUS
COUNTERS
(CONTINUE)
• Exercise:
• Determine the MOD for each configuration shown below?
16
MR1
MR2
Q0
Q1
Q2
Q3
CP0
CP1
74293
MR1
MR2
Q0
Q1
Q2
Q3
CP0
CP1
74293
1 0 1
3 2 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

17. CHIP FOR ASYNCHRONOUS
COUNTERS
(CONTINUE)
• Determine the MOD for each configuration shown below?
17
MR1
MR2
Q0
Q1
Q2
Q3
CP0
CP1
74293

18. ASYNCHRONOUS COUNTERS
• Disadvantages of Asynchronous Counters:-
• Propagation delay is severe for larger MOD of counters, especially at the MSB.
• Existence of ‘glitch’ is inevitable for MOD  2N counters.
• Difficult to design random counters (i.e:- to design circuit that counts numbers
in the random sequence 6→4→7→2→1→6→4→7→2→1→6→4….)
• Disadvantages can be overcome by:::::
SYNCHRONOUS COUNTERS.
18

19. SYNCHRONOUS COUNTERS
• For synchronous counters, all the flip-flops are using the same
CLOCK signal.Thus, the output would change synchronously.
• Procedure to design synchronous counter are as follows:-
STEP 1: Obtain the State Diagram.
STEP 2: Obtain the Excitation Table using state transition table for any particular FF (JK or D).
Determine number of FF used.
STEP 3: Obtain and simplify the function of each FF input using K-Map.
STEP 4: Draw the circuit.
19

20. SYNCHRONOUS COUNTERS
• Design a MOD-4 synchronous up-counter, using JK FF.
STEP 1: Obtain the State transition Diagram
20
0
1
2
3
00
01
10
11
Binary

21. SYNCHRONOUS COUNTERS
STEP 2: Obtain the Excitation table.Two JK FF are used.
21
Present State Next State
A B A B JA KA JB KB
0 0 0 1 0 X 1 X
0 1 1 0 1 X X 1
1 0 1 1 X 0 1 X
1 1 0 0 X 1 X 1
OUTPUT TRANSITION
QN QN+1
FF INPUT
J K
0 → 0 0 X
0 → 1 1 X
1 → 0 X 1
1 → 1 X 0
Excitation table

22. SYNCHRONOUS COUNTERS
STEP 3: Obtain the simplified function using K-Map
22
B
A 0 1
0 0 1
1 X X
JA = B
B
A 0 1
0 X X
1 0 1
KA = B
B
A 0 1
0 1 X
1 1 X JB = 1
B
A 0 1
0 X 1
1 X 1 KB = 1

23. SYNCHRONOUS COUNTERS
STEP 4: Draw the circuit diagram
23
JB Q
KB
Q
CLK
1
JA Q
KA
Q
CLK
B (LSB) A (MSB)

24. SYNCHRONOUS COUNTERS
• Design a MOD-4 synchronous down-counter, using JK FF?
STEP 1: Obtain the State transition Diagram
24
0
3
2
1
00
11
10
01
Binary

25. SYNCHRONOUS COUNTERS
• Obtain the Excitation table.Two JK FF are used.
25
Present St. Next St.
A B A B JA KA JB KB
0 0 1 1 1 X 1 X
0 1 0 0 0 X X 1
1 0 0 1 X 1 1 X
1 1 1 0 X 0 X 1
OUTPUT TRANSITION
QN QN+1
FF INPUT
J K
0 → 0 0 X
0 → 1 1 X
1 → 0 X 1
1 → 1 X 0

26. SYNCHRONOUS COUNTERS
• Obtain the simplified function using K-Map
26
B
A 0 1
0 1 0
1 X X
JA =B’
B
A 0 1
0 X X
1 1 0
KA =B’
B
A 0 1
0 1 X
1 1 X
JB = 1
B
A 0 1
0 X 1
1 X 1
KB =1

27. SYNCHRONOUS COUNTERS
• Draw the circuit diagram
27
JB Q
KB
Q
CLK
JA Q
KA
Q
CLK
B
A

28. 28
3-Bit Synchronous Counter using JK F/F

29. 29
K-map for Inputs

30. 30

31. MOD-8
31

32. 32

33. 33
}

34. MODULO-10 UP/DOWN COUNTER USINGT
FFS
• Step 1: The number of flip flops:A modulo-10 counter has 10 states and so it
requires 4 FFs.
• 4-FFs can have 16 states. So out of 16, six states (1010 through 1111) are invalid.
The entries for excitations corresponding to invalid states are don’t cares. For
selecting up and down modes a control or mode signal is required. Let us say it
counts up when the mode signal M=1 and counts down when M=0.The clock signal
is applied to all the FFs simultaneously.
• Step 2: The state diagram:The state diagram of the mod-10 up/down counter is
drawn.
• Step 3: The type of flip flops and the excitation table:T flip flops are selected
and the excitation table of the modulo-10 up/down counter usingT FFs
34

35. STATE DIAGRAM
35

36. 36
PS MOD
E
NS Required excitations
Q4 Q3 Q2 Q1 M Q4 Q3 Q2 Q1 T4 T3 T2 T1
0 0 0 0 0 1 0 0 1 1 1 0 1
0 0 0 0 1 0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 0 0 1 0 0 1 1
0 0 1 0 1 0 0 1 1 0 0 0 1
0 0 1 1 0 0 0 1 0 0 0 0 1
0 0 1 1 1 0 1 0 0 0 0 1 1
0 1 0 0 0 0 0 1 1 0 0 1 1
0 1 0 0 1 0 1 0 1 0 0 0 1
0 1 0 1 0 0 1 0 0 0 0 0 1
0 1 0 1 1 0 1 1 0 0 0 1 1
0 1 1 0 0 0 1 0 1 0 0 1 1
0 1 1 0 1 0 1 1 1 0 0 0 1
0 1 1 1 0 0 1 1 0 0 0 0 1
0 1 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 1 1 1 1 1 1 1
1 0 0 0 1 1 0 0 1 0 0 0 1
1 0 0 1 0 1 0 0 0 0 0 0 1
1 0 0 1 1 0 0 0 0 1 0 0 1

37. 37

38. 38

39. MODULO-9 SYNCHRONOUS
COUNTER USINGT FFS
• Step 1: The number of flip flops: counting sequence for a modulo-9
counter is 0000,0001,0010,0011,0100,0101,0110,0111,1000,0000,…
• It has 9 states. So it requires 4 FFs
• (9<=24). 4 flip flops can have 16 states. 7 states 1001, 1010, 1100, 1101,
1110, and 1111 are invalid.The entries for excitation corresponding to
invalid states are don’t cares.
• Step 2: The states diagram:The states diagram for the mod-9 counter
is drawn
• Step 3: The type of flip flops and the excitation table:T flip flops
are selected and the excitation table of a mod-9 counter using T FFs is
drawn.
39

40. PS NS Required Excitations
Q4 Q3 Q2 Q1 Q4 Q3 Q2 Q1 T4 T3 T2 T1
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 1
0 0 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 1
0 1 0 1 0 1 1 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 0 0 1 0 0 0
40

41. 41
Step 4: The minimal expressions: The K-maps for excitation
T4,T3,T2, and T1 in term of the outputs of the FFs Q4,Q3,Q3 and Q1,
their minimization and the minimal expression for excitation
obtained

42. 42
 A shift register counter is a shift register whose output
being fed back (connected back) to the serial input. This
shift register would count the state in a unique sequence!
 Two types of shift register counter:-
 The ring counter
 The Johnson counter
Shift Register Counters

43. 43
Ring Counter
Q3 Q2 Q1 Q0

44. 44
Ring Counter (continue)
0 0 0 1
1 0 0 0
0 1 0 0
0 0 1 0

45. 45
Ring Counter (continue)

46. 46
Ring Counter (continue)
❑Ring counters are used to
construct “One-Hot” counters
❑It can be constructed for any
desired MOD number
❑A MOD-N ring counter uses
N flip-flops connected in the
arrangement as shown in fig.
In general ring-counter will
require more flip-flops than a
binary counter for the same
MOD number

47. 47
Ring Counter (continue)

48. 48
Johnson Counter
Or Twisted-ring counter
❑Johnson counter constructed exactly like a normal ring counter
except that the inverted output of the last flip-flop is fed back to
first flip-flop

49. 49
Johnson Counter (Continue)
A
B
C
0 1 1 1
0 0 1 1
0 0 0 1

50. 50
Johnson Counter (Continue)

51. Thankyou