Sequntial logic design

III B.TECH I SEMESTER
DIGITAL IC APPLICATIONS
UNIT-5
RAGHU INSTITUTE OF TECHNOLOGY
AUTONOMOUS
DEPARTMENT OF ELECTRONICS AND COMMUNICATIONS ENGINEERING
Prepared by
Mr. M.PAVAN KUMAR
Assistant Professor

REFERENCES
 Digital Design Principles & Practices – John F. Wakerly, PHI/
Pearson Education Asia, 3rd Ed., 2005.
 Fundamentals of Digital Logic with VHDL Design- Stephen
Brown, ZvonkoVranesic, McGrawHill, 3rd Edition.
 Digital IC Applications- A.P Godse, D.A Godse, Technical
Publications.
Mr. M.PAVAN KUMAR DICA ECE Department RIT 2

➢ CONTENTS
 SSI Latches and Flipflops
 Ring Counter
 Johnson Counter
 n-synchronous Counter design
 Shift Registers
 Modeling of Sequential IC design
3Mr. M.PAVAN KUMAR DICA ECE Department RIT

4
Sequential Circuits
 A sequential circuit is one whose outputs depend not only
on its current inputs, but also on the past sequence of inputs.
 In other words, sequential circuits must be able to
”remember” (i.e., store) the past history of the inputs in order
to produce the present output.
 The information about the previous inputs history is called the
state of the system.
 A circuit that uses n binary state variables to store its past
history can take up to 2n
different states.
 Since n is always finite, sequential circuits are also called
finite state machines (FSM).
Mr. M.PAVAN KUMAR DICA ECE Department RIT

5
How can we remember …?
 The key to build storage circuits is feedback !!
Cg
A storage element
from Physics
ε
ε)v(tv(t)
limC
Δt
Δv
limC
dt
dv
Ci(t)
0εg
0Δtgg
−−
===
→
→
A storage element model
from Calculus
1 0 1
0 1 0
time
t t+δ t+2δ
Unfortunately caps are not ideal
they lose charge !!!

6
In short, sequential circuits are …
 circuits consisting of ordinary gates and feedback
loops
X1
X2
•
•
•
Xn
switching
network
Z1
Z2
•
•
•
Zn

7
"remember"
"load"
"data"
"stored value"
"0"
"1"
"stored value"
The simplest sequential circuit
 Two inverters and a feedback loop form a “static” storage cell
 The cell will hold value as long as it has power applied
 How to get a new value into the storage cell?
 selectively break feedback path
 load new value into cell D latch
(= state)
bistable cell

8
Analog analysis of the bistable cell
Vout2Vout1 = Vin2Vin1
Vin1 = Vout2

9
Latches and Flip-Flops
 The two most popular varieties of storage cells used to build
sequential circuits are: latches and flip-flops.
Latch: level sensitive storage element
Flip-Flop: edge triggered storage element
 Common examples of latches:
S-R latch, S-R latch, D latch (= gated D latch)
 Common examples of flip-flops:
D-FF, D-FF with enable, Scan-FF, JK-FF, T-FF

SSI LATCH
10
(hold)
(reset)
(set)
(forbidden)
SR latch using nor :
R S Qn Qn+1
0 0 0 Qn (0)
0 0 1 Qn (1)
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0/1 *
Excitation Table:
Qn Qn+1 R S
0 0 × 0
0 1 0 1
1 0 1 0
1 1 × ×

SR Latch using NAND Gate:
11
SN(t) RN(t) Q(t) Q(t+∆)
1 1 0 0
1 1 1 1
1 0 0 0
1 0 1 0
0 1 0 1
0 1 1 1
0 0 0 X
0 0 1 X
hold
reset
set
not allowed

12
D Latch (= Transparent Latch)
=
G D Q Qbar
0 × Last Q Last Q
bar
1 0 0 1
1 1 1 0

13
SSI FLIPFLOP’S
 Clocks are regular periodic signals used to specify state changes

14
D Flip-Flop (positive edge triggered)
Notice: the little triangle !
Functional
Table
Truth Table More compact
Truth Table
D Q+
0 0
1 1
Next state equation:
CLK
D
Q
inputs sampled on rising edge; outputs change after rising edge
D Qn Qn+1
0 0 0
0 1 0
1 0 1
1 1 1
Qn+1 = D

15
Timing Behavior of a DFF
(positive edge triggered)

16
Setup and hold times for an
edge-triggered DFF

17
Minimum clock period T ?
Example with T = 9 ns
tpINV = 2 ns
tpFF = 5 ns
tsuFF = 3 ns
Example with T = 15 ns
T = 9 ns T = 15 ns

18
Minimum clock period T ? (cont’d)
tpINV = 2 ns
tpFF = 5 ns
tsuFF = 3 ns
Tmin = 10 ns
Observation:
thFF doesn’t affect this calculation

19
D Flip-Flop (negative edge triggered)
inputs sampled on falling edge; outputs change after falling edge

20
DFF with asynchronous preset and clear

21
DFF with asynchronous preset and clear

22
DFF with enable
D
Do not even think about it !!!
D
CK
0
1
Q
Q’
D
EN
CLK
Reliable alternative

23
DFF with enable (cont’d)

24
Scan DFF

25
Design for testability: scan chains

26
JK Flip Flop (rising edge triggered)
=
Functional Table
J K Qn Qn+1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Next state equation:

27
Toggle Flip Flop (rising edge triggered)
CLK
T
Q
T
CK
Q
Q’
T
CLK
Truth Table More compact
Truth Table
T Q+
0 Q
1 Q’

28
Activity
 Design a JK-FF and a T-FF using D-FFs
 Design a D-FF and a T-FF using JK-FFs
 Design a D-FF and a JK-FF using T-FFs

29
Summary of latches and flip flops

30
behavior is the same unless input changes
while the clock is high
D Q
CLK
positive
edge-triggered
flip-flop
D Q
G
CLK
transparent
(level-sensitive)
latch
D
CLK
QFF
Qlatch
Comparison of latches and flip-flops
QFF
Qlatch

31
Type When inputs are sampled When output is valid
unclocked always propagation delay from input
latch change
level-sensitive clock high ( ∏ ) propagation delay from input
latch (Tsu/Th around falling change or clock edge
edge of clock) (whichever is later)
master-slave clock high ( ∏ ) propagation delay from falling
flip-flop (Tsu/Th around falling edge of clock
edge of clock)
positive clock L-to-H transition (↑) propagation delay from rising
edge-triggered (Tsu/Th around rising edge of clock
flip-flop edge of clock)
Comparison of latches and flip-flops
(cont’d)

VHDL program for D latch

VHDL program for D flipflop using if-then

D flip-flop using Asynchronous input
34

35
 SSI LATCHES and Flip-Flops

Introduction to Counters
36
 In General Flipflop it will store one bit of information at a time. But more than one bit
storing we are not supposed to prefer Flipflops. Then go for REGISTER.
 Register is used for storing more no. of bits and also shifting data which is in the form
of 1s / 0s.
 A counter is a Register, capable of counting the number of clock pulses arriving at its
clock input. And a specified sequence of states appears as the counter output.
COUNTER’S
Synchronous / Parallel Counter Asynchronous / Ripple Counter

4-Bit Asynchronous counter/
4-Bit ripple up counter by using negative edge trigger

Synchronous Counter
38
 When counter is clocked such that each flipflop in the counter is triggered at
the same time, the counter is called as synchronous counter.
 Designing of Synchronous counter follows sequence of steps:
Step1: Identify the range of states we have and no. of flipflops we want to design
Step2: Identify, which type of flipflop is suitable to your specification
Step3: Write the excitation table for that flipflop
Step4: Derive the excitation circuit by using Boolean expression derived from the
K-map

3-Bit Synchronous Counter
39
Qn Qn+1 J K
0 0 0 ×
0 1 1 ×
1 0 × 1
1 1 × 0
Qc Qb Qa Qc
+
Qb
+
Qa
+
Ja Ka Jb Kb Jc Kc
0 0 0 0 0 1 1 × 0 × 0 ×
0 0 1 0 1 0 × 1 1 × 0 ×
0 1 0 0 1 1 1 × × 0 0 ×
0 1 1 1 0 0 × 1 × 1 1 ×
1 0 0 1 0 1 1 × 0 × 0 ×
1 0 1 1 1 0 × 1 1 × 0 ×
1 1 0 1 1 1 1 × × 0 0 ×
1 1 1 0 0 0 × 1 × 1 × 1

4-Bit Synchronous Counter

Ring Counter
41
 A looping process or cyclic process of counting clock pulses in the manner of
Synchronous is known as Ring Counter.
 looping process apply by using Feedback system.
 n-Bit ring counter counts n-clock pluses with n-no.of flipflop’s.

Rotation moment of counting Clock pulses
42

4-Bit 4-State Ring counter using IC 74*194
43

Johnson Counter/ Twisted Ring Counter
44
 The Johnson Ring Counter or “Twisted Ring Counters”, is another shift
register with feedback exactly the same as the standard Ring Counter above,
except that this time the inverted output Q of the last flip-flop is now connected
back to the input D of the first flip-flop.
 this type of ring counter is that it only needs half the number of flip-flops
compared to the standard ring counter then its modulo number is halved.
 “n-stage” Johnson counter will circulate a single data bit giving sequence
of 2n different states and can therefore be considered as a “mod-2n counter”.

45
2-bit Johnson Ring Counter :

4-Bit Johnson Counter using IC 74*194

Decade Binary counter IC 7490
47
Count Outputs
QD QC QB QA
0 L L L L
1 L L L H
2 L L H L
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L
9 H L L H

Internal Architecture of 7490 (Decade Binary Counter)
48
FFB FFC FFD
Mod-5 Counter
FFA
S(2)S(1)R(2)R(1)Input
Clk B
Input
Clk A
QA QB QC QD
Set inputsReset inputs
IC 7490
S(2)S(1)R(2)R(1)
A
B
QA QB QC QD
Clock

Divide by 20 counter using 7490
49
IC 7490 (1)
S(2)S(1) R(2)R(1)
A
B
QA QB QC QD
Clock
IC 7490 (2)
S(2)S(1) R(2)R(1)
A
B
QA QB QC QD
Clock
Tens DigitUnits Digit
QD QC QB QA
0 0 1 0
QD QC QB QA
0 0 0 0
 We know that IC 7490 is a Decade or mod-10 counter. Then we need two ic’s. The counter will go through
states 0-19 and should be reset on state 20. i.e. at place of 6th
binary digit 32 we connect to reset. Then it
will counts upto 20. after it will shows 0.

50
IC 7490 (1)
S(2)S(1) R(2)R(1)
A
B
QA QB QC QD
Clock
IC 7490 (2)
S(2)S(1) R(2)R(1)
A
B
QA QB QC QD
Clock
Tens DigitUnits Digit
QH QG QF QE
1 0 0 1 (9)
QD QC QB QA
0 1 1 0 (6)
 We know that IC 7490 is a Decade or mod-10 counter. Then we need two cascading of ic’s leads to divide
by 100 counter. The counter will go through states 0-99 and should be reset on after 96. i.e. after the bit
1001 0110 after it will shows 0.

4 Bit Ripple counter 7492/93
51
FFB FFC FFD
Mod-6 Counter
FFA
R(2)R(1)Input
Clk B
Input
Clk A
QA QB QC QD
Reset inputs

52
IC 7490
R(2)R(1)
A
B
QA QB QC QD
Clock

4-Bit Synchronous Binary Counter 74*163
53
CLK
CLR
LD
ENP
ENT
A
B
C
D
Q0
Q1
Q2
Q3
RCO

Excess-3 Decimal counter using 74*163
54
CLK
CLR
LD
ENP
ENT
A
B
C
D
Q0
Q1
Q2
Q3
RCO
5v 1
1
0
0

Shift Registers
55
 Binary Information in a register can be moved from stage to stage within the register or
Out of the register upon application of clock pulses.
 This type of Bit movement or shifting is essential for certain arithmetic and logical
operations used in Microprocessors.
Serial shift right, then out : Serial shift left, then out :
Parallel shift in : Parallel shift out :
Rotate Right : Rotate Left :

Modes of operation of Shift register
56
 we have 4 types of modes of operations in shift registers.
(i) Serial in serial out Shift Register
(ii) Serial in parallel Out Shift Register
(iii) Parallel in serial out Shift Register
(iv) Parallel in parallel out shift register

57
(i) Serial in serial out Shift Register (SISO):
 The input to this register is given in serial fashion i.e. one bit after the other
through a single data line and the output is also collected serially.
CLK Q2 Q1 Q0
initial 0 0 0
0 0 0
1 0 0
1 1 0
0 1 1
0 0 1
N
N-1

58
 When we transfer data in SISO manner then we taken output at last flipfliop. i.e.
Q0 and input as first flipflop i.e Q2.
 Time consumed for clock to store N bits is = [ N+N-1] * T
= [ 2N-1]*T , N= no.of Bits, T= clock duration
 Suppose we have 2msec duration for one cycle. Then for 4-bit it will have
= [2(4)-1]*2
= 14msec.
Note: for GATE

59
(ii) Serial in parallel Out Shift Register :
CLK Q2 Q1 Q0
initial 0 0 0
0 0 0
1 0 0
1 1 0

60
 When we transfer data in SIPO manner then we taken output at each and every
flipfliop. i.e. Q0,Q1,Q2
 Time consumed for clock to store N bits is = [ N ] * T
N= no.of Bits, T= clock duration
 Suppose we have 2msec duration for one cycle. Then for 4-bit it will have
= (4)*2 = 8msec.
Note: for GATE
 Total time consumed by the clock to store the bits in SISO manner = [2N-1]*T
 Total time consumed by the clock to store the bits in SIPO manner= N*T

61
(iii) Parallel in serial out Shift Register :

62
 WHEN I/P IS 0 THEN IT IS IN LOAD MODE
 WHEN I/P IS 1 THEN IT IS IN SHIFT MODE

63
(iv) Parallel in parallel out shift register :
• In this register, the input is given in parallel and the output also collected in
parallel. The clear (CLR) signal and clock signals are connected to all the 4 flip
flops.

Universal Shift Register
64
 A register is capable of shifting in one direction only. i.e either right shift or left
shift. Hence it is named as unidirectional shift register.
 A register is capable of shifting in both the direction. i.e. right shift and left shift.
Hence it is named as bi-directional shift register or Universal Shift Register.
This register can perform three types of operations, stated below.
•Parallel loading
•Shifting left
•Shifting right.

65
S1 S0 Operation
0 0 No change
0 1 Shift-Right
1 0 Shift-Left
1 1 Parallel Load

4-Bit Bi-Directional Universal Shift Register IC
74LS194
66
74LS194
VCC
Q0
Q1
Q2
Q3
CLK
S1
S0
CLR
DSR
D0
D1
D2
D3
DSL
GND
Mode INPUTS OUTPUTS
Clk CLR S1 S0 Dsr Dsl Dn Q0 Q1 Q2 Q3
Rst × 0 × × × × × 0 0 0 0
Shift Left 1 1 1 0 × 0 × Q1 Q2 Q3 0
1 1 1 0 × 1 × Q1 Q2 Q3 1
Shift
Right
1 1 0 1 0 × × 0 Q0 Q1 Q2
1 1 0 1 1 × × 1 Q0 Q1 Q2
Parllel
Load
1 1 1 1 × × Dn D0 D1 D2 D3
Hold ×` 1 0 0 × × × Q0 Q1 Q2 Q3
Parallel data

VHDL Codes for Registers
67
 VHDL Code for 4-Bit Register : Here this register is an asynchronous reset/clear states.
This code is same as D-Flipflop with asynchronous reset except the input D and output Q are
Declared as multibit signals.
Library IEEE;
USE IEEE.STD_LOGIC_1164.all;
Entity reg4 is
Port ( D : in std_logic_vector (3 down to 0);
rst, clk : in std_logic ;
Q : out std_logic_vector (3 down to 0));
End reg4;
Architecture behav of reg4 is
Begin
Process (rst,clk)
Begin
If rst = ‘0’ then
Q <= “0000” ;
Elsif clock’event and clk=‘1’ then
Q <= D ;
End If ;
End Process;
End behav ;

68
 VHDL code for 4-Bit Shift Register : (Shift Right)
Library IEEE ;
USE IEEE.std_logic_1164.all ;
Entity shiftright is
Port ( clock: in std_logic ;
I : in std_logic ;
Q : Buffer std_logic_vector (3 down to 0)) ;
End shiftright ;
Architecture behav of shiftright is
Begin
Process
Begin
Wait Until clock’event and clock=‘1’ ;
Q(0) <= Q(1) ;
Q(1) <= Q(2) ;
Q(2) <= Q(3) ;
Q(3) <= I ;
End Process ;
End behav

69
 VHDL code for 4-Bit Parallel Access Shift Register : (PIPO)
Library IEEE ;
USE IEEE.std_logic_1164.all ;
Entity PIPO is
Port ( P : in std_logic_vector (3 down to 0) ;
clock: in std_logic ;
Load, I : in std_logic ;
Q : Buffer std_logic_vector (3 down to 0)) ;
End PIPO ;
Architecture behav of PIPO is
Begin
Process
Begin
Wait Until clock’event and clock=‘1’ ;
If Load = ‘1’ Then
Q <= P ;
else
Q(0) <= Q(1) ;
Q(1) <= Q(2) ;
Q(2) <= Q(3) ;
Q(3) <= I ;
End Process ;
End behav

Sequntial logic design

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