VLSI Design Sequential circuit design

P R E P A R E D B Y
V . T H A M I Z H A R A S A N
A S S I S T A N T P R O F E S S O R
D E P A R T M E N T O F E C E
E R O D E S E N G U N T H A R E N G I N E E R I N G
C O L L E G E
Sequential circuit design
1
11: Sequential Circuits

Sequencing static circuits
2
 Combinational logic
 output depends only on current inputs
 Sequential logic
 output depends on current and previous inputs
 Requires flip flop or latch(memory element )=>hold the data
called tokens or state
 Ex: FSM, pipeline
CL
clk
in out
clk clk clk
CL CL
PipelineFinite State Machine

Sequencing Cont.
3
 If tokens moved through pipeline at constant speed,
no sequencing elements will be needed
 Ex: fiber-optic cable
 Light pulses (tokens) are sent down cable
 Next pulse sent before first reaches end of cable
 No need for hardware to separate pulses
 But dispersion sets min time between pulses
 This is called wave pipelining in circuits
 In most circuits, dispersion is high
 Delay fast tokens so they don’t catch slow ones.

Sequencing Overhead
4
 We need to delay fast tokens, so that they don't catch
up with slow tokens
 Use flip-flops to delay fast tokens so they move
through exactly one stage each cycle.
 Inevitably adds some delay to the slow tokens
 Makes circuit slower than just the logic delay
 Called sequencing overhead or clocking overhead

Sequencing Methods
5
 Flip-flops
 2-Phase Latches
 Pulsed Latches
Flip-Flops
FlopLatch
Flop
clk
1
2
p
clk clk
Latch
Latch
p
p
1
1
2
2-PhaseTransparentLatchesPulsedLatches
Combinational Logic
Combinational
Logic
Combinational
Logic
Combinational Logic
Latch
Latch
Tc
Tc
/2
tnonoverlap
tnonoverlap
tpw
Half-Cycle 1 Half-Cycle 1

Timing Diagrams
6
Flop
A
Y
tpd
Combinational
Logic
A Y
D Q
clk clk
D
Q
Latch
D Q
clk
clk
D
Q
tcd
tsetup thold
tccq
tpcq
tccq
tsetup
thold
tpcq
tpdq
tcdq
tpd
Logic Propagation Delay
tcd
Logic Cont. Delay
tpcq
Latch/Flop Clk->Q Prop. Delay
tccq
Latch/Flop Clk->Q Cont. Delay
tpdq
Latch D->Q Prop. Delay
tcdq
Latch D->Q Cont. Delay
tsetup
Latch/Flop Setup Time
thold
Latch/Flop Hold Time
Contamination and
Propagation Delays

Max-Delay: Flip-Flops
7
F1
F2
clk
clk clk
Combinational Logic
Tc
Q1 D2
Q1
D2
tpd
tsetup
tpcq
 setup
sequencing overhead
pd c pcqt T t t  
If combinational logic delay
high
mismatch the setup and
hold time, samples the
wrong value
setup time failure or MAX -
delay failure
Solved by => changing the combinational logic to faster or increasing the clock
period
TC≥tpcq+tpd+tsetup

Max Delay: 2-Phase Latches
8
Tc
Q1
L1
1
2
L2
L3
1
1
2
Combinational
Logic 1
Combinational
Logic 2
Q2 Q3D1 D2 D3
Q1
D2
Q2
D3
D1
tpd1
tpdq1
tpd2
tpdq2
TC≥tpdq1+tpd1+ tpdq2+tpd2
Tpd= tpd1+ tpd2≤ TC-(2tpdq)
Sequencing
overhead

Max Delay: Pulsed Latches
9
Tc
Q1 Q2D1 D2
Q1
D2
D1
p
p
p
Combinational Logic
L1
L2
tpw
(a) tpw
> tsetup
Q1
D2
(b) tpw
< tsetup
Tc
tpd
tpdq
tpcq
tpd
tsetup
 setup
sequencing overhead
max ,pd c pdq pcq pwt T t t t t   
TC≥ max(tpdq+tpd,tpcq+tpd+tsetup-tpw)

Min-Delay: Flip-Flops
10
holdcd ccqt t t 
CL
clk
Q1
D2
F1
clk
Q1
F2
clk
D2
tcd
thold
tccq
If hold time is large &
the contamination delay small .
The data can incorrectly propagate
through two successive elements
on clock edge
This called race condition ,hold
time failure or min delay faliure
It can only be fixed by
redesigning the logic ,not by
slowing the clock.

Min-Delay: 2-Phase Latches
11
1, 2 hold nonoverlapcd cd ccqt t t t t  
CL
Q1
D2
D2
Q1
1
L1
2
L2
1
2
tnonoverlap
tcd
thold
tccq
Hold time reduced by
nonoverlap time sufficiently
large
Paradox: latch seems to
require twice the overall
logic contamination delay
as compared to FF

Min-Delay: Pulsed Latches
12
holdcd ccq pwt t t t  
CL
Q1
D2
Q1
D2
p tpw
p
L1
p
L2
tcd
thold
tccq
Hold time=> increased by
pulse width

Time Borrowing
13
 In a flop-based system:
 Data leave on rising edge
 Must setup before next rising edge
 If it arrives late, system fails
 If it arrives early, time is wasted
 Flops have hard edges– sharply define the cycle.
 In a latch-based system
 Data leave on first rising edge
 But does not have setup until falling edge of the clock on the receiving
latch
 Long cycle of logic can borrow time into next half cycle or stage
 loops may borrow time internally but must complete within the cycle
completes in one cycle.

Time Borrowing Example
14
Latch
Latch
Latch
Combinational Logic
Combinational
Logic
Borrowing time across
half-cycle boundary
Borrowing time across
pipeline stage boundary
(a)
(b)
Latch
LatchCombinational Logic
Combinational
Logic
Loops may borrow time internally but must complete within the cycle
1
2
1
1
1
2
2

How Much Borrowing?
15
Q1
L1
1
2
L2
1
2
Combinational Logic 1
Q2D1 D2
D2
Tc
Tc
/2
Nominal Half-Cycle 1 Delay
tborrow
tnonoverlap
tsetup
 borrow setup nonoverlap
2
cT
t t t  
2-Phase Latches
borrow setuppwt t t 
Pulsed Latches

Benefits of time borrowing
 Intentional time borrowing
Designer can more easily balance logic between half cycles and
pipeline stage.
Balancing can take place during the circuit style rather than change in
the micro architecture.
 Opportunistic time borrowing
Designer carefully equalize the delay in each stage at design time .
delays can differ from one stage to other in fabricated chip due to
environmental and process variation.
time borrowing => the slow cycles can opportunistically borrow time
from faster ones .
16

Clock Skew
17
 clock skew (TSkew)
is the difference in the arrival time
between two sequentially-adjacent
registers.
 Clocks really have uncertainty in
arrival time
 Decreases maximum propagation
delay
 Increases minimum contamination
delay
 Decreases time borrowing

Another example
tsu
th
Q0 Q0
reg tpd
clk0

clk1
clk0
clk1
tskew
18

Skew: Flip-Flops
19
F1
F2
clk
clk clk
Combinational Logic
Tc
Q1 D2
Q1
D2
tskew
CL
Q1
D2
F1
clk
Q1
F2
clk
D2
clk
tskew
tsetup
tpcq
tpdq
tcd
thold
tccq
 setup skew
sequencing overhead
hold skew
pd c pcq
cd ccq
t T t t t
t t t t
   
  

Skew: Latches
20
Q1
L1
1
2
L2
L3
1
1
2
Combinational
Logic 1
Combinational
Logic 2
Q2 Q3D1 D2 D3
 
 
sequencing overhead
1 2 hold nonoverlap skew
borrow setup nonoverlap skew
2
,
2
pd c pdq
cd cd ccq
c
t T t
t t t t t t
T
t t t t
 
   
   
2-Phase Latches
 
 
setup skew
sequencing overhead
hold skew
borrow setup skew
max ,pd c pdq pcq pw
cd pw ccq
pw
t T t t t t t
t t t t t
t t t t
    
   
  
Pulsed Latches

Circuit design of latches and flip flops
 Conventional CMOS latches =>built using
pass transistor or tristate buffer
1. Very simple transparent latch=> using single
transistor
 But the output does not swing rail to rail
 It never rise above vdd-vt
 The output floats when the latch is opaque. also
long time opaque means suffers from leakage
D Q

21

Cont.,
2.Using CMOS transmission gate:
 To offer full rail to rail output.
 It requires complementary clock.
3. Adds output as an inverter.
 So that the state node x as an inverter
isolated from the noise
4.Buffered input:
D Q


D


X
Q
D Q


C2MOS
structure
22

Cont.,
 Modern process ,sub threshold
leakage is large enough that
dynamic nodes retain their values
for only short time.
 Practical latches need to be
staticized =>adding feedback to
prevent the output from floating
 But create a noise at output due to
feedback




QD
X


QD
X


23

Cont.,
Very robust transparent latch:
 All nodes produces full rail output
 Static noise isolated from the output noise
Robust transparent latch with
inverting output


Q
D
X






Q
D
X
Jamb latch:
Reduce the clock load, save two
transistor by using weak
inverter in place of tri state.
24

Conventional CMOS flip-flops
 Dynamic FF from
back to back dynamic
latches
D Q




X
D




X
Q
Q




25

Transmission gate and NORA dynamic flip flop
 Φ falls ,both the clock and its complement are
momentarily low .
 If the skew is too large=> leading to incorrect operation.
26

Two phase non overlapping clocks
27

Reset
 Synchronous reset :
synchronous reset signal will only affect or reset the
state of the flip-flop on the active edge of the clock.
 Asynchronous reset :
An asynchronous reset will affect or reset the state of
the flip-flop asynchronously i.e. no matter what the
clock signal is.
28

Resettable latches and flip flop
D




Q
Q




reset
D






Q

D
reset


Q


D
reset
reset


reset
SynchronousResetAsynchronousResetSymbol
Flop
D Q
LatchD Q
reset reset
 


Q
reset
29

Enabled latches and Flip flop
D Q
Latch
D Q
en
en


Latch
D
Q

0
1
en
Latch
D Q
 en
D
Q

0
1
en
D Q
 en
Flop
Flop
Flop
Symbol Multiplexer Design Clock Gating Design
30

Klass semidynamic flip flop (SDFF)
31

CONT.,
X remains high because
n2 off
X starts to fall low.
32

CONT.,
33

CONT.,
34

True single phase clock latches
 TSPC latches and FFs replace the inverter –transmission
gate or C2MOS stage with pair of stages requiring only
the clock not its complement
35

True single phase clock flip flop
36

CONT.,
37

Differential flip flop
38

CONT.,
39

Static sequencing element methodology
40

Introduction
 No. of issues designer take care to when selecting
sequential circuits.
 Until 0.5 or 0.35 μm =>leakage relatively low
 Leakage => usually worst during burn in testing at
elevated temperature and voltage.
 Designer has forced to build design for test (DFT)
features into sequencing elements.
 Mostly use scan based testing.
41

Cont.,
 Another challenge is clock distribution
Very difficult to distribute a single clock across a
large die that gets into all sequencing elements at
nearly the same time.
 Delayed clk, complementary clk, pulses are
generated internally.
42

Choice of elements
 1.flip flops
 FF=>fairly high sequencing overhead , but are
popular , they are so simple.
 Many ASIC methodologies use FFS exclusively for
pipelines and state machine.
2. Pulsed latches:
 It is faster than FFs and offer some time borrowing
capability at expense of greater hold time.
 fewer clocked transistor=>low power consumption.
 Long hold time => unsuitable for pipeline stage
 If the speed is not important we can use FFS.
43

CONT.,
 3. Transparent latches:
Lower sequencing overhead than FFs
They permit nearly half cycle of time borrowing
44

Low power sequential design
45
 FFs and latches are normally clocked every cycle.
Both core latch and clock distribution network must be
carefully analyzed to achieve low dynamic power
 Keep device size – small inside the latch
 Minimize the number of clocked transistors.
 Pulsed latch –attractive => because fewer clocked
transistor than two phase latches & FFs
 Also tradeoff between testability and power
consumption.
 Clock gating effectively used
turn off certain section– it does not required
certain time intervals.

Two phase timing types
46
 Signal can belong to either phase1 or phase2 =>three
classes:1.stable,2.valid,3.qulified clock.
 Stable(_s1):if it settles to a value before Φ1 rises &
remains constant until after Φ1 falls.
 valid(_v1): if it settles to a value before Φ1 falls &
remains constant until after Φ1 falls..
 qualified clock(_q1):if it either rises and falls like
Φ1 or remains low for the entire cycle

Cont.,
48
 Phase1 requires _s1 or _v1 input =>
produces _s2 output—output settles before Φ1 rise
 Phase2 requires _s2 or _v2 input =>
produces _s1 output
 Qualified clocks are formed by AND of a clock phase.
 Qualified clock must be stable—there is no glitches.

Characterizing sequencing element delay
49

Sequencing dynamic circuits
50

Traditional domino circuits
51
 clk—high ,1st half cycle evalevates,2nd precharges
 Clk-low,1st precharge,2nd evaluates
 This is ping-pong approach, the precharge does not
appear in the critical path.
 In latches, hold the. data during precharge period,
next evaluates.

Traditional domino circuits with skew
52
 Data launched into first dynamic gate –rising edge of the clk—setup the
data before falling of the clk.
 Clk skew --cut the time available for computation in each cycle.
 In latch Clk skew is worst than FFs
Also Traditional domino ckt suffer
from imbalanced logic.
Gates can not borrow time into
the next half cycle– fraction of gate
delay at the end of each half cycle may
be wasted

Skew tolerant domino circuits
53
 Traditional domino ckt—high sequencing overhead—
have hard edge. In each half cycle.
 1st domino gate does not evaluate before rising edge
of the clk—but result must be setup the latch before
falling.
 Cut the overhead by – if we remove the latch
 Latch serves two function:
1.to prevent non monotonic signals from entering the next domino gate while
it evaluates
2.To hold the results of the half cycle while it precharge and the next half cycle
evaluates

Cont.,
54
 In domino –all the signals are monotonic--so 1st function unnecessary
after next half cycle has sufficient to evaluate
Ф1 falls –a precharge high
& b precharge low
When Ф2 rises –input of 1st domino gate
already fall , so c never discharge the
ckt loses the information
When Ф2 rises –while b still holds its
correct value
Ф1 falls –b precharge low ,c holds its
value
non overlapping overlapping

Time borrowing in skew –tolerant domino
circuits
55

Two phase skew tolerant domino
56
If contamination delay
is small –race condition
occur

OTB domino
57

4-phase skew tolerant domino
58

Clock generator 4-phase skew tolerant domino
59

VLSI Design Sequential circuit design

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