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  1. 1. Design and Implementation of VLSI Systems (EN1600) Lecture 22: Sequential Circuit Design (1/2)S. Reda EN160 SP’08
  2. 2. Sequential circuits • Purpose of time: we need time to order events • Combinational logic – output depends on current inputs • Sequential logic – events are ordered using the clock signal – output depends on current and previous inputs – memory elements are used to store the results of the events or states (certainly if they will be used in the future). Inputs Outputs COMBINATIONAL LOGIC Current State Next state Registers Q D CLKS. Reda EN160 SP’08
  3. 3. Differences between latches and flipflops • Latches are level sensitive • Flipflops are edge triggeredS. Reda EN160 SP’08
  4. 4. Basic latch and bistability requirement A A V i 2 5 V o1 V i 2 5 V o1 C C B B V i 1 5 V o2 V i 1 5 V o2 d dS. Reda EN160 SP’08
  5. 5. 1. Latch Design • Pass Transistor Latch • Pros φ + Tiny D Q + Low clock load • Cons – Vt drop – nonrestoring – output noise sensitivity – dynamic – diffusion inputS. Reda EN160 SP’08
  6. 6. 1. Latch Design φ • Transmission gate D Q + No Vt drop - Requires inverted clock φ φ • Inverting buffer X + Restoring D Q + Fixes either φ φ • Output noise sensitivity • Or diffusion input D Q – Inverted output φS. Reda EN160 SP’08
  7. 7. 1. Latch Design φ • Tristate feedback X D Q + Static φ – Output noise sensitivity φ – Diffusion input φ • Static latches are now essential • Buffered input φ + Fixes diffusion input X D Q + Noninverting φ φ - Output noise sensitivity φS. Reda EN160 SP’08
  8. 8. 1. Latch Design • Buffered output Q φ + Output noise sensitivity eliminated X D • Widely used in standard cells φ φ + Very robust (most important) - Rather large φ - Rather slow (1.5 – 2 FO4 delays) - High clock loading φ Q X • Datapath latch D φ φ + Smaller, faster - unbuffered input φS. Reda EN160 SP’08
  9. 9. 2. Flip-flop design • Flip-flop is built as pair of back-to-back latches φ φ X D Q φ φ φ φ Q X D Q φ φ φ φ φ φS. Reda EN160 SP’08
  10. 10. 2. Latch/Flip-flop with ENABLE • Enable: ignore clock when en = 0 – Mux: increase latch D-Q delay – Clock Gating: increase in setup time, skew Symbol Multiplexer Design Clock Gating Design φ en φ φ D 1 Latch Latch Latch D Q Q D Q 0 en en φ en φ φ D 1 Flop Q 0 Flop Flop D Q D Q en enS. Reda EN160 SP’08
  11. 11. 2. Latch/Flip-flop with SET/RESET • Set forces output high when enabled • Flip-flop with asynchronous set and reset [Figure from Baker]S. Reda EN160 SP’08
  12. 12. Setup and hold times CLK t Register tsu thold D Q D D ATA CLK STABL E t tc 2 q Q D ATA STABL E t • Setup time: the minimum time that the data input must be valid before clock transition • Hold time: the minimum time that the data input must be valid after the clock transitionS. Reda EN160 SP’08
  13. 13. Sequencing timing terminology tpd Logic Prop. Delay tpdq Latch D-Q Prop Delay tcd Logic Cont. Delay tpcq Latch D-Q Cont. Delay tpcq Latch/Flop Clk-Q Prop Delay tsetup Latch/Flop Setup Time tccq Latch/Flop Clk-Q Cont. Delay thold Latch/Flop Hold TimeS. Reda EN160 SP’08