Digital Design with CPLD Applications and VHDL

1. Logic Functions and Gates

2.  The three basic logic functions are:
◦ AND
◦ OR
◦ NOT
2

3.  Logic functions can be represented:
 algebraically
 using truth tables
 using electronic circuits.
3

4.  Uses Boolean algebra.
 Boolean variables have two states (binary).
 Boolean operators include AND, OR, and NOT.
4

5.  Defines the output of a function for every
possible combination of inputs.
 A system with n inputs has 2n possible
combinations.
5

6.  Uses logic gates to perform Boolean algebraic
functions.
 Gates can be represented by schematic
symbols.
 Symbols can be either distinctive-shape or
rectangular-outline.
6

7.  Uses different graphic representations for
different logic functions.
 Uses a bubble (a small circle) to indicate a
logical inversion.
7

8.  All functions are shown in rectangular
form with the logic function indicated by
standard notation inside the rectangle.
 The notation specifying the logic function
is called the qualifying symbol.
 Inversion is indicated by a 1/2 arrowhead.
8

9.  One input and one output.
 The output is the opposite logic level of the
input.
 The output is the complement of the input.
9

10.  Inversion is indicated by a bar over the
signal to be inverted.
10
AY 

11.  Called a NOT gate or, more usually, an
INVERTER.
 Distinctive-shape symbol is a triangle with
inversion bubble.
 Rectangular-shape symbol uses “1” and the
inversion 1/2 arrowhead.
11

12. 12

13.  Two or more inputs, one output.
 Output is HIGH only when all of the inputs are
HIGH.
 Output is LOW whenever any input is LOW.
13

14. A B Y
0 0 0
0 1 0
1 0 0
1 1 1
14

15.  AND symbol is “•” or nothing at all.
15
ABY
BAY



16.  Called an AND gate.
 Distinctive-shape symbol uses AND
designation.
 Rectangular-shape symbol use “&” as
designator.
16

17. 17

18. 18

19. A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
19

20.  Two or more inputs, one output.
 Output is HIGH whenever one or more input
is HIGH.
 Output is LOW only when all of the inputs are
LOW.
20

21. A B Y
0 0 0
0 1 1
1 0 1
1 1 1
21

22.  OR symbol is “+”.
 Y = A + B
22

23.  Called an OR gate.
 Distinctive-shape symbol uses OR
designation.
 Rectangular-shape symbol uses “” as
designator.
23

24. 24

25.  The logic level defined as “ON” for a circuit.
 When a logic HIGH is “ON”, the signal is
active-HIGH.
 When a logic LOW is “ON”, the signal is
active-LOW.
25

26.  Generated by inverting the output of the AND
function.
 Output is HIGH whenever any input is LOW.
 Output is LOW only when all inputs are HIGH.
26

27. A B Y
0 0 1
0 1 1
1 0 1
1 1 0
27

28.  Uses AND with an inversion overbar.
28
BAY 

29.  Called a NAND gate.
 Uses the AND symbol with inversion on.
29

30. 30

31.  Generated by inverting the output of the OR
function.
 Output is HIGH only when all inputs are LOW.
 Outputs is LOW whenever any input is HIGH.
31

32. A B Y
0 0 1
0 1 0
1 0 0
1 1 0
32

33.  Uses OR with an inversion overbar.
33
BAY 

34.  Called a NOR gate.
 Uses OR symbol with inversion on the output.
34

35. 35

36.  3 Input NAND:
 3 Input NOR:
36
CBAY 
CBAY 

37. CBA A B C
0 0 0 1 1
0 0 1 1 0
0 1 0 1 0
0 1 1 1 0
1 0 0 1 0
1 0 1 1 0
1 1 0 1 0
1 1 1 0 0
CBA 
37
CBA

38.  Two inputs, one output.
 Output is HIGH when one, and only one, input
is HIGH.
 Output is LOW when both inputs are equal –
both HIGH or both LOW.
38

39. 39

40. A B Y
0 0 0
0 1 1
1 0 1
1 1 0
40

41.  Two inputs, one output.
 Output is HIGH when both inputs are equal –
both HIGH or both LOW.
 Output is LOW when one, and only one, input
is HIGH.
41

42. 42

43. A B Y
0 0 1
0 1 0
1 0 0
1 1 1
43

44.  A NAND gate can be represented by an AND
gate with inverted output.
 A NAND gate can be represented by an OR
gate with inverted inputs.
44

45. 45

46.  A NOR gate can be represented by an OR gate
with inverted output.
 A NOR gate can be represented by an AND
gate with inverted inputs.
46

47.  Change an AND function to an OR function
and an OR function to an AND function.
 Invert the inputs.
 Invert the outputs.
47

48.  Break the line and change the sign
48
BABA 
BABA 

49.  The following are two common errors
associated with DeMorgan’s Theorem:


49
BABA 
BABA 

50.  Any INPUT or OUTPUT that has a BUBBLE is
considered as active LOW.
 Any INPUT or OUTPUT that has no BUBBLE is
considered as active HIGH.
50

51. 
 At least one input HIGH makes the output
LOW.

 All inputs LOW make the output HIGH.
51
BAY 
BAY 

52. 52

53.  Provides a logic HIGH or LOW depending on
switch position.
 Commonly used types include normally-open
pushbutton, normally-closed pushbutton,
single-pole single-throw, and single-pole
double-throw.
53

54. 54

55. 55

56.  Two-pole push button allows for normally
HIGH and normally LOW levels from the same
switch.
56

57. 57

58.  Used to indicate the status of a digital output.
 Has two terminals the anode and the cathode.
 If the anode is approximately 1.5 V greater
than the cathode, current flows and the LED
illuminates.
58

59. 59

60. 60

61.  Used to provide a visual indication of a logic
state.
 Can be wired to display active-HIGH or
active-LOW.
61

62. 62

63. 63

64.  The input to a gate that allows the output to
respond to other inputs.
 A logic LOW for an OR or NOR gate, a logic
HIGH for an AND or NAND gate.
64

65.  The input to a gate that forces the output to
ignore any other input.
 A logic HIGH for an OR or NOR gate, a logic
LOW for an AND or NAND gate.
65

66. 66

67. 67

68. 68

69. 69

70. 70

71. 71

72. Control AND OR NAND NOR XOR XNOR
A = 0 Y = 0 Y = B Y = 1 Y = B
A = 1 Y = B Y = 1 Y = 0 Y = BBY 
BY 
BY 
72
BY 

73.  Three output states, HIGH, LOW and high-
impedance.
 Requires a separate input to control which
output state is selected.
73

74. 74

75. 75

76.  Used to connect multiple outputs together.
 Used in controlling the operation of buses.
76

77. 77

78.  Contains two groups of four non-inverting
tri-state buffers.
 Each group is controlled by a separate
enable input.
78
G

79. 79

80.  Integrated Circuits (ICs) contain many
components in a single package.
 Several packaging options are available.
 One common package is called dual-in-line
(DIP).
80

81. 81

82.  One common form is transistor-transistor
logic, called TTL.
 The other common form is Complementary
Metal-Oxide Semiconductor, called CMOS.
82

83. Part Number Logic Family
74LS00 Low-power Schottky TTL
74ALS00 Advanced low-power Schottky TTL
74F00 FAST TTL
74HC00 High-speed CMOS
74CT00 High-speed CMOS (TTL-compatible inputs)
74LVX00 Low-voltage CMOS
74ABT00 Advanced BiCMOS (TTL/CMOS hybrid)
83

84.  Standard form is 74XXFF, where 74 is the
logic family identifier, XX is the logic family
member and FF identifies the specific logic
function.
 SN74ALS00N
84

85.  PLCC - plastic lead chip carrier
 SOIC - small outline integrated circuit
 TSSOP – thin shrink small outline package
 QFP – quad flat pack
 DIP – dual inline package
 BGA – ball grid array
85

86. 86

87.  Can be mounted on the surface of a circuit
board or mounted in a socket.
 Pins are equally distributed on four sides.
 Pin 1 placed on the center of one of the
rows, as indicated by a dot.
 Pins number counterclockwise from this
point.
87

88. 88