SlideShare a Scribd company logo
1 of 25
DIGITAL LOGIC
 What is gate?
 The Basic Gates
 NOT gate
 OR gate
 AND gate
 Universal Logic Gates
 NOR gate
 NAND gate
1
Presented by,
M.Madhu Bala
GATES
 A digital circuit having one or more input signals but only one
output signal is called a gate.
 Connecting the basic gates in different ways makes it
possible to produce circuits.
 Gates are often called logic circuits.
 The basic gates can be used to produce any digital system.
 The three basic logic circuits are
 the inverter (NOT)
 the OR gate and
 the AND gate
2
THE INVERTER (NOT GATE)
 A NOT gate has one input signal and one output signal.
 The output Y of NOT gate is always complement of input A.
 In equation form
Y= NOT A Y=A‘ Y=A
 There are only two possible voltage levels (low and high) associated
with a digital circuit. This fits with the binary number system (0&1)
 This is often referred to as two-state operation.
 In the positive logic,
 the higher voltage level is assigned the binary value 1 (H=1)
 the lower voltage level is assigned the binary value 0 .(L=0)
3
A Y=A’
L H
H L
A Y=A’
0 1
1 0
Logic Circuit of NOT gate
Truth Table
THE INVERTER (NOT GATE)
TTL NOT Gates
Pinout diagram of a 7404 hex inverter
 This IC contains six inverters.
 After applying +5 V to pin 14 and grounding pin 7, you can connect
any or all inverters to other Transistor–Transistor Logic(TTL) devices.
4
OR GATE
 An OR gate has two or more input signals but only one output
signal.
 It is called an OR gate because the output voltage is high if any or
all of the input voltages are high.
 In Boolean equation form
Y = A OR B Y = A + B
The '+' sign represents the logic operation OR
 The number of rows in a truth table equals 2n, where n is the
number of inputs
5
Logic Circuit of OR gate
A B Y=A+B
0 0 0
0 1 1
1 0 1
1 1 1
Truth Table
Three- input OR gate
 The inputs are A, B, and C.
 When all inputs are low, the output is low.
 If any input is high, the output will be high.
 Boolean Equation Form:
Y = A+B+C
6
OR GATE (CONT..)
A B C Y=A+B+C
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1Logic Circuit of 3-input OR gate
Truth Table
TTL OR Gates
This digital IC contains four 2-input OR gates inside a 14-
pin DIP.
After connecting a supply voltage of +5 V to pin 14 and a
ground to pin 7, you can connect one or more of the OR
gates to other TTL devices.
7
OR GATE (CONT.)
Timing diagram for 2-input OR gate
 The input voltages drive pins 1 and 2 of a 7432.
 The output (pin 3) is low only when both inputs are low.
 The output is high the rest of the time.
8
OR GATE (CONT..)
 The AND gate has a high output only when all inputs are high.
otherwise the output will be low.
 AND gate also known as all-or-nothing gate.
 In Boolean equation form
Y =A AND B Y=A.B Y=AB
The '.' sign represents the logic AND operation.
9
AND GATE
A B Y=AB
0 0 0
0 1 0
1 0 0
1 1 1Logic Circuit of AND gate
Truth Table
Three- input AND gate
 The inputs are A, B, and C.
 When all inputs are high, the output is high.
 If even one input is low, the output is in the low state.
 In Boolean equation form:
Y=A.B.C Y=ABC
10
AND GATE (CONT..)
A B C Y=ABC
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
Logic Circuit of AND gate
Truth Table
TTL AND Gates
 This digital IC contains four 2-input AND gates.
 After connecting a supply voltage of +5V to pin 14 and a ground to
pin 7, you can connect one or more of the AND gates to other TTL
devices.
 TTL AND gates are also available in triple 3-input and dual 4-input
packages.
11
AND GATE (CONT..)
Timing diagram for a 2-input AND gate
The input voltages drive pins 1 and 2 of a 7408.
the output (pin 3) is high only when both inputs are high.
The output is low the rest of the time.
12
AND GATE (CONT..)
The NAND & NOR gates are called universal gates because
they can perform all the logical operations of basis gates like
AND, OR, NOT.
13
Universal Logic Gate
 The circuit of NOR gate is a circuit of OR gate followed by an inverter
 The output of NOR gate is
Y=A+B
 NOR Gates also called a NOT-OR gate.
 All inputs must be low to get a high output.
 If any input is high, the output is low.
14
NOR GATE
Logic Circuit of NOR Gates
Abbreviated form Standard form IEEE form
Truth Table
A B Y=(A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Pin- out Diagram of NOR gate
15
NOR GATE (CONT.)
Bubbled AND Gate
 Bubbled AND Gate inverters on the input lines of an AND gate.
 The output of bubbled AND gate and NOR gate are identical.
 Therefore, these two circuits are equivalent and thus
interchangeable.
 The output of bubbled AND gate is represented as
Y= A . B
16
NOR GATE (CONT.)
Abbreviated form Standard form
Truth Table
A B A’ B’ Y=A’.B’
0 0 1 1 1
0 1 1 0 0
1 0 0 1 0
1 1 0 0 0
Logic Circuit of Bubbled AND Gates
De Morgan's First Theorem
NOR gate : Y=(A+B)’
bubbled AND gate : Y=A’B’
 The outputs are equal for the same inputs, so that (A+B)’ = A’B’
 The complement of a sum equals the product of the complements.
This identity is known as De Morgan’s, first theorem.
 This can also be proved by comparing the truth tables of NOR and
bubbled AND gates.
 Three input NOR gate and three input bubbled AND gate are
identical and it can write, (A+ B + C)' = A'B'C'
 This equivalence can be extended to gates or circuits for larger
number of inputs, too.
17
NOR GATE (CONT.)
NOT from NOR
 To get a NOT gate, tie inputs of NOR gate together so that there is
only one input to the circuit.
 If input is 0, then both the inputs to NOR gate are 0 that gives output
1.
 Similarly, if input is 1, both the inputs to NOR gate are 1 that gives
output 0.
 Therefore the output of circuit is complement of its input and thus
gives NOT operation.
18
NOR GATE (CONT.)
OR from NOR
 To get a OR gate, two NOR gates are used.
 The first NOR gate performs usual NOR operation.
 The second NOR gate performs as NOT gate and inverts the
NOR logic to OR
19
NOR GATE (CONT.)
A+B
AND from NOR
 To get a AND gate, three NOR gates are used.
 The first and second NOR gate performs as NOT gate.
 NOT gates are replaced by NOR equivalent. Since NOR gate is
NOT operation followed by OR we invert the
 output of example 2.3, shown in Fig. 2.9b to get output of this
circuit. Thus output of circuit in Fig. 2.2 lc is
 high only when both the inputs are high and it functions like an
AND gate.
20
NOR GATE (CONT.)
 The circuit of NAND gate is a circuit of AND gate followed by an
inverter
 The output of NAND gate is
Y=AB "Y equals NOT A AND B"
 NAND Gates also called a NOT-AND gate.
 All inputs must be high to get a low output.
 If any input is low, the output is high.
21
NAND GATE
Logic Circuit of NAND Gate
Abbreviated form Standard form IEEE form
Truth Table
A B AB Y=AB
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
Pin- out Diagram of NAND gate
22
NAND GATE (CONT.)
Bubbled OR Gate
 Bubbled OR Gate inverters on the input lines of an OR gate.
 The output of bubbled OR gate and NAND gate are identical.
 Therefore, these two circuits are equivalent and thus
interchangeable.
 The output of bubbled OR gate is represented as
Y=A+B
23
NAND GATE (CONT.)
A B A B Y=A+B
0 0 1 1 1
0 1 1 0 1
1 0 0 1 1
1 1 0 0 0
Abbreviated form Standard form
Truth TableLogic Circuit of Bubbled OR Gate
De Morgan's Second Theorem
NAND Gate :(AB)’
Bubbled OR Gate : Y=A’+B’
 The outputs are equal for the same inputs, so that (AB)’ = A’+B’
 The complement of a product equals the sum of the complements.
This identity is known as De Morgan’s second theorem.
 This can also be proved by comparing the truth tables of NAND gate
and bubbled OR gate.
 Three input NAND gate and three input bubbled OR gate are identical
and it can write, (ABC)' = A’+B‘+C’
 This equivalence can be extended to gates or circuits with any number
of inputs.
24
NAND GATE (CONT.)
THANK YOU
25

More Related Content

What's hot

Logic simplification sop and pos forms
Logic simplification sop and pos formsLogic simplification sop and pos forms
Logic simplification sop and pos formsManesh T
 
Adder substracter
Adder substracterAdder substracter
Adder substracterWanNurdiana
 
Digital Logic Circuits
Digital Logic CircuitsDigital Logic Circuits
Digital Logic Circuitssathish sak
 
Introduction to Counters
Introduction to CountersIntroduction to Counters
Introduction to CountersISMT College
 
Combinational circuits
Combinational circuits Combinational circuits
Combinational circuits DrSonali Vyas
 
Adder & subtractor (Half adder, Full adder, Half subtractor, Full subtractor)
Adder & subtractor (Half adder, Full adder, Half subtractor, Full subtractor)Adder & subtractor (Half adder, Full adder, Half subtractor, Full subtractor)
Adder & subtractor (Half adder, Full adder, Half subtractor, Full subtractor)ISMT College
 
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.Satya P. Joshi
 
Exclusive OR GAte
Exclusive OR GAteExclusive OR GAte
Exclusive OR GAteawais ahmad
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuitsSARITHA REDDY
 

What's hot (20)

Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuits
 
Combinational circuit
Combinational circuitCombinational circuit
Combinational circuit
 
Logic simplification sop and pos forms
Logic simplification sop and pos formsLogic simplification sop and pos forms
Logic simplification sop and pos forms
 
Adder substracter
Adder substracterAdder substracter
Adder substracter
 
Digital Logic Circuits
Digital Logic CircuitsDigital Logic Circuits
Digital Logic Circuits
 
Introduction to Counters
Introduction to CountersIntroduction to Counters
Introduction to Counters
 
Logic gates presentation
Logic gates presentationLogic gates presentation
Logic gates presentation
 
Chapter 4: Combinational Logic
Chapter 4: Combinational LogicChapter 4: Combinational Logic
Chapter 4: Combinational Logic
 
Combinational circuits
Combinational circuits Combinational circuits
Combinational circuits
 
Adder and subtrctor DLD
Adder and subtrctor  DLDAdder and subtrctor  DLD
Adder and subtrctor DLD
 
Adder & subtractor (Half adder, Full adder, Half subtractor, Full subtractor)
Adder & subtractor (Half adder, Full adder, Half subtractor, Full subtractor)Adder & subtractor (Half adder, Full adder, Half subtractor, Full subtractor)
Adder & subtractor (Half adder, Full adder, Half subtractor, Full subtractor)
 
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
Logic gates - AND, OR, NOT, NOR, NAND, XOR, XNOR Gates.
 
Exclusive OR GAte
Exclusive OR GAteExclusive OR GAte
Exclusive OR GAte
 
Combinational circuit
Combinational circuitCombinational circuit
Combinational circuit
 
Encoder.pptx
Encoder.pptxEncoder.pptx
Encoder.pptx
 
Boolean algebra & logic gates
Boolean algebra & logic gatesBoolean algebra & logic gates
Boolean algebra & logic gates
 
13 Boolean Algebra
13 Boolean Algebra13 Boolean Algebra
13 Boolean Algebra
 
Combinational circuits
Combinational circuitsCombinational circuits
Combinational circuits
 
MULTIPLEXER
MULTIPLEXERMULTIPLEXER
MULTIPLEXER
 
Sequential circuits
Sequential circuitsSequential circuits
Sequential circuits
 

Similar to Digital logic

Lecture 04-Digital logic gates.pptx
Lecture 04-Digital logic gates.pptxLecture 04-Digital logic gates.pptx
Lecture 04-Digital logic gates.pptxWilliamJosephat1
 
digital electronics .pptx
digital electronics .pptxdigital electronics .pptx
digital electronics .pptxAjaykumar967485
 
assignment_mathematics.pptx
assignment_mathematics.pptxassignment_mathematics.pptx
assignment_mathematics.pptxAravindaAKumar1
 
chapter 3 Boolean algebra (2).pptx
chapter 3 Boolean algebra (2).pptxchapter 3 Boolean algebra (2).pptx
chapter 3 Boolean algebra (2).pptxRithinA1
 
physics investigatory on logic gates
physics investigatory on logic gatesphysics investigatory on logic gates
physics investigatory on logic gatesMoviesBuzz1
 
1,basic and derived logic gates.pdf
1,basic and derived logic gates.pdf1,basic and derived logic gates.pdf
1,basic and derived logic gates.pdfDamotTesfaye
 
M. FLORENCE DAYANA/unit - II logic gates and circuits.pdf
M. FLORENCE DAYANA/unit - II logic gates and circuits.pdfM. FLORENCE DAYANA/unit - II logic gates and circuits.pdf
M. FLORENCE DAYANA/unit - II logic gates and circuits.pdfDr.Florence Dayana
 
Digital logic Gates of Computer Science
Digital logic Gates of Computer ScienceDigital logic Gates of Computer Science
Digital logic Gates of Computer ScienceAnil Kumar Prajapati
 
Semiconductor Devices Class 12 Part-4
Semiconductor Devices Class 12 Part-4Semiconductor Devices Class 12 Part-4
Semiconductor Devices Class 12 Part-4Self-employed
 
solids_and_semiconductor_devices_4.ppt
solids_and_semiconductor_devices_4.pptsolids_and_semiconductor_devices_4.ppt
solids_and_semiconductor_devices_4.pptUmeshPatil149
 
Solids_And_Semiconductor_Devices_4.ppt
Solids_And_Semiconductor_Devices_4.pptSolids_And_Semiconductor_Devices_4.ppt
Solids_And_Semiconductor_Devices_4.pptJosephMuez2
 
boolean algrebra and logic gates in short
boolean algrebra and logic gates in shortboolean algrebra and logic gates in short
boolean algrebra and logic gates in shortRojin Khadka
 

Similar to Digital logic (20)

Lecture 04-Digital logic gates.pptx
Lecture 04-Digital logic gates.pptxLecture 04-Digital logic gates.pptx
Lecture 04-Digital logic gates.pptx
 
Logic gates
Logic gatesLogic gates
Logic gates
 
logic gates
logic gateslogic gates
logic gates
 
digital electronics .pptx
digital electronics .pptxdigital electronics .pptx
digital electronics .pptx
 
Deld lab manual
Deld lab manualDeld lab manual
Deld lab manual
 
assignment_mathematics.pptx
assignment_mathematics.pptxassignment_mathematics.pptx
assignment_mathematics.pptx
 
chapter 3 Boolean algebra (2).pptx
chapter 3 Boolean algebra (2).pptxchapter 3 Boolean algebra (2).pptx
chapter 3 Boolean algebra (2).pptx
 
physics investigatory on logic gates
physics investigatory on logic gatesphysics investigatory on logic gates
physics investigatory on logic gates
 
1,basic and derived logic gates.pdf
1,basic and derived logic gates.pdf1,basic and derived logic gates.pdf
1,basic and derived logic gates.pdf
 
M. FLORENCE DAYANA/unit - II logic gates and circuits.pdf
M. FLORENCE DAYANA/unit - II logic gates and circuits.pdfM. FLORENCE DAYANA/unit - II logic gates and circuits.pdf
M. FLORENCE DAYANA/unit - II logic gates and circuits.pdf
 
Digital logic Gates of Computer Science
Digital logic Gates of Computer ScienceDigital logic Gates of Computer Science
Digital logic Gates of Computer Science
 
Logic gates
Logic gatesLogic gates
Logic gates
 
Logic gates (1)
Logic gates (1)Logic gates (1)
Logic gates (1)
 
Semiconductor Devices Class 12 Part-4
Semiconductor Devices Class 12 Part-4Semiconductor Devices Class 12 Part-4
Semiconductor Devices Class 12 Part-4
 
solids_and_semiconductor_devices_4.ppt
solids_and_semiconductor_devices_4.pptsolids_and_semiconductor_devices_4.ppt
solids_and_semiconductor_devices_4.ppt
 
Solids_And_Semiconductor_Devices_4.ppt
Solids_And_Semiconductor_Devices_4.pptSolids_And_Semiconductor_Devices_4.ppt
Solids_And_Semiconductor_Devices_4.ppt
 
Class 12th Logic Gates
Class 12th Logic GatesClass 12th Logic Gates
Class 12th Logic Gates
 
Chapter+13.ppt
Chapter+13.pptChapter+13.ppt
Chapter+13.ppt
 
Logic gates 07 11-2014
Logic gates 07 11-2014Logic gates 07 11-2014
Logic gates 07 11-2014
 
boolean algrebra and logic gates in short
boolean algrebra and logic gates in shortboolean algrebra and logic gates in short
boolean algrebra and logic gates in short
 

More from Madhu Bala

Internet of Things (IoT)
Internet of Things (IoT)Internet of Things (IoT)
Internet of Things (IoT)Madhu Bala
 
Operating system
Operating systemOperating system
Operating systemMadhu Bala
 
Greedy Algorithm - Knapsack Problem
Greedy Algorithm - Knapsack ProblemGreedy Algorithm - Knapsack Problem
Greedy Algorithm - Knapsack ProblemMadhu Bala
 
GRAPH APPLICATION - MINIMUM SPANNING TREE (MST)
GRAPH APPLICATION - MINIMUM SPANNING TREE (MST)GRAPH APPLICATION - MINIMUM SPANNING TREE (MST)
GRAPH APPLICATION - MINIMUM SPANNING TREE (MST)Madhu Bala
 
Divide and conquer - Quick sort
Divide and conquer - Quick sortDivide and conquer - Quick sort
Divide and conquer - Quick sortMadhu Bala
 
GPRS Technology
GPRS TechnologyGPRS Technology
GPRS TechnologyMadhu Bala
 
Algorithm - Introduction
Algorithm - IntroductionAlgorithm - Introduction
Algorithm - IntroductionMadhu Bala
 
Data structure - Graph
Data structure - GraphData structure - Graph
Data structure - GraphMadhu Bala
 
Smoothing Filters in Spatial Domain
Smoothing Filters in Spatial DomainSmoothing Filters in Spatial Domain
Smoothing Filters in Spatial DomainMadhu Bala
 

More from Madhu Bala (10)

Internet of Things (IoT)
Internet of Things (IoT)Internet of Things (IoT)
Internet of Things (IoT)
 
Operating system
Operating systemOperating system
Operating system
 
Greedy Algorithm - Knapsack Problem
Greedy Algorithm - Knapsack ProblemGreedy Algorithm - Knapsack Problem
Greedy Algorithm - Knapsack Problem
 
GRAPH APPLICATION - MINIMUM SPANNING TREE (MST)
GRAPH APPLICATION - MINIMUM SPANNING TREE (MST)GRAPH APPLICATION - MINIMUM SPANNING TREE (MST)
GRAPH APPLICATION - MINIMUM SPANNING TREE (MST)
 
Divide and conquer - Quick sort
Divide and conquer - Quick sortDivide and conquer - Quick sort
Divide and conquer - Quick sort
 
GPRS Technology
GPRS TechnologyGPRS Technology
GPRS Technology
 
Algorithm - Introduction
Algorithm - IntroductionAlgorithm - Introduction
Algorithm - Introduction
 
4G technology
4G technology4G technology
4G technology
 
Data structure - Graph
Data structure - GraphData structure - Graph
Data structure - Graph
 
Smoothing Filters in Spatial Domain
Smoothing Filters in Spatial DomainSmoothing Filters in Spatial Domain
Smoothing Filters in Spatial Domain
 

Recently uploaded

Crystal Structure analysis and detailed information pptx
Crystal Structure analysis and detailed information pptxCrystal Structure analysis and detailed information pptx
Crystal Structure analysis and detailed information pptxachiever3003
 
TechTAC® CFD Report Summary: A Comparison of Two Types of Tubing Anchor Catchers
TechTAC® CFD Report Summary: A Comparison of Two Types of Tubing Anchor CatchersTechTAC® CFD Report Summary: A Comparison of Two Types of Tubing Anchor Catchers
TechTAC® CFD Report Summary: A Comparison of Two Types of Tubing Anchor Catcherssdickerson1
 
CCS355 Neural Networks & Deep Learning Unit 1 PDF notes with Question bank .pdf
CCS355 Neural Networks & Deep Learning Unit 1 PDF notes with Question bank .pdfCCS355 Neural Networks & Deep Learning Unit 1 PDF notes with Question bank .pdf
CCS355 Neural Networks & Deep Learning Unit 1 PDF notes with Question bank .pdfAsst.prof M.Gokilavani
 
Past, Present and Future of Generative AI
Past, Present and Future of Generative AIPast, Present and Future of Generative AI
Past, Present and Future of Generative AIabhishek36461
 
Transport layer issues and challenges - Guide
Transport layer issues and challenges - GuideTransport layer issues and challenges - Guide
Transport layer issues and challenges - GuideGOPINATHS437943
 
Risk Management in Engineering Construction Project
Risk Management in Engineering Construction ProjectRisk Management in Engineering Construction Project
Risk Management in Engineering Construction ProjectErbil Polytechnic University
 
multiple access in wireless communication
multiple access in wireless communicationmultiple access in wireless communication
multiple access in wireless communicationpanditadesh123
 
Unit7-DC_Motors nkkjnsdkfnfcdfknfdgfggfg
Unit7-DC_Motors nkkjnsdkfnfcdfknfdgfggfgUnit7-DC_Motors nkkjnsdkfnfcdfknfdgfggfg
Unit7-DC_Motors nkkjnsdkfnfcdfknfdgfggfgsaravananr517913
 
complete construction, environmental and economics information of biomass com...
complete construction, environmental and economics information of biomass com...complete construction, environmental and economics information of biomass com...
complete construction, environmental and economics information of biomass com...asadnawaz62
 
Energy Awareness training ppt for manufacturing process.pptx
Energy Awareness training ppt for manufacturing process.pptxEnergy Awareness training ppt for manufacturing process.pptx
Energy Awareness training ppt for manufacturing process.pptxsiddharthjain2303
 
Indian Dairy Industry Present Status and.ppt
Indian Dairy Industry Present Status and.pptIndian Dairy Industry Present Status and.ppt
Indian Dairy Industry Present Status and.pptMadan Karki
 
Gurgaon ✡️9711147426✨Call In girls Gurgaon Sector 51 escort service
Gurgaon ✡️9711147426✨Call In girls Gurgaon Sector 51 escort serviceGurgaon ✡️9711147426✨Call In girls Gurgaon Sector 51 escort service
Gurgaon ✡️9711147426✨Call In girls Gurgaon Sector 51 escort servicejennyeacort
 
Instrumentation, measurement and control of bio process parameters ( Temperat...
Instrumentation, measurement and control of bio process parameters ( Temperat...Instrumentation, measurement and control of bio process parameters ( Temperat...
Instrumentation, measurement and control of bio process parameters ( Temperat...121011101441
 
Software and Systems Engineering Standards: Verification and Validation of Sy...
Software and Systems Engineering Standards: Verification and Validation of Sy...Software and Systems Engineering Standards: Verification and Validation of Sy...
Software and Systems Engineering Standards: Verification and Validation of Sy...VICTOR MAESTRE RAMIREZ
 
Sachpazis Costas: Geotechnical Engineering: A student's Perspective Introduction
Sachpazis Costas: Geotechnical Engineering: A student's Perspective IntroductionSachpazis Costas: Geotechnical Engineering: A student's Perspective Introduction
Sachpazis Costas: Geotechnical Engineering: A student's Perspective IntroductionDr.Costas Sachpazis
 
Arduino_CSE ece ppt for working and principal of arduino.ppt
Arduino_CSE ece ppt for working and principal of arduino.pptArduino_CSE ece ppt for working and principal of arduino.ppt
Arduino_CSE ece ppt for working and principal of arduino.pptSAURABHKUMAR892774
 
Work Experience-Dalton Park.pptxfvvvvvvv
Work Experience-Dalton Park.pptxfvvvvvvvWork Experience-Dalton Park.pptxfvvvvvvv
Work Experience-Dalton Park.pptxfvvvvvvvLewisJB
 
Internet of things -Arshdeep Bahga .pptx
Internet of things -Arshdeep Bahga .pptxInternet of things -Arshdeep Bahga .pptx
Internet of things -Arshdeep Bahga .pptxVelmuruganTECE
 

Recently uploaded (20)

Crystal Structure analysis and detailed information pptx
Crystal Structure analysis and detailed information pptxCrystal Structure analysis and detailed information pptx
Crystal Structure analysis and detailed information pptx
 
TechTAC® CFD Report Summary: A Comparison of Two Types of Tubing Anchor Catchers
TechTAC® CFD Report Summary: A Comparison of Two Types of Tubing Anchor CatchersTechTAC® CFD Report Summary: A Comparison of Two Types of Tubing Anchor Catchers
TechTAC® CFD Report Summary: A Comparison of Two Types of Tubing Anchor Catchers
 
CCS355 Neural Networks & Deep Learning Unit 1 PDF notes with Question bank .pdf
CCS355 Neural Networks & Deep Learning Unit 1 PDF notes with Question bank .pdfCCS355 Neural Networks & Deep Learning Unit 1 PDF notes with Question bank .pdf
CCS355 Neural Networks & Deep Learning Unit 1 PDF notes with Question bank .pdf
 
Past, Present and Future of Generative AI
Past, Present and Future of Generative AIPast, Present and Future of Generative AI
Past, Present and Future of Generative AI
 
Transport layer issues and challenges - Guide
Transport layer issues and challenges - GuideTransport layer issues and challenges - Guide
Transport layer issues and challenges - Guide
 
Risk Management in Engineering Construction Project
Risk Management in Engineering Construction ProjectRisk Management in Engineering Construction Project
Risk Management in Engineering Construction Project
 
multiple access in wireless communication
multiple access in wireless communicationmultiple access in wireless communication
multiple access in wireless communication
 
Unit7-DC_Motors nkkjnsdkfnfcdfknfdgfggfg
Unit7-DC_Motors nkkjnsdkfnfcdfknfdgfggfgUnit7-DC_Motors nkkjnsdkfnfcdfknfdgfggfg
Unit7-DC_Motors nkkjnsdkfnfcdfknfdgfggfg
 
complete construction, environmental and economics information of biomass com...
complete construction, environmental and economics information of biomass com...complete construction, environmental and economics information of biomass com...
complete construction, environmental and economics information of biomass com...
 
Energy Awareness training ppt for manufacturing process.pptx
Energy Awareness training ppt for manufacturing process.pptxEnergy Awareness training ppt for manufacturing process.pptx
Energy Awareness training ppt for manufacturing process.pptx
 
Designing pile caps according to ACI 318-19.pptx
Designing pile caps according to ACI 318-19.pptxDesigning pile caps according to ACI 318-19.pptx
Designing pile caps according to ACI 318-19.pptx
 
Indian Dairy Industry Present Status and.ppt
Indian Dairy Industry Present Status and.pptIndian Dairy Industry Present Status and.ppt
Indian Dairy Industry Present Status and.ppt
 
Gurgaon ✡️9711147426✨Call In girls Gurgaon Sector 51 escort service
Gurgaon ✡️9711147426✨Call In girls Gurgaon Sector 51 escort serviceGurgaon ✡️9711147426✨Call In girls Gurgaon Sector 51 escort service
Gurgaon ✡️9711147426✨Call In girls Gurgaon Sector 51 escort service
 
Instrumentation, measurement and control of bio process parameters ( Temperat...
Instrumentation, measurement and control of bio process parameters ( Temperat...Instrumentation, measurement and control of bio process parameters ( Temperat...
Instrumentation, measurement and control of bio process parameters ( Temperat...
 
Software and Systems Engineering Standards: Verification and Validation of Sy...
Software and Systems Engineering Standards: Verification and Validation of Sy...Software and Systems Engineering Standards: Verification and Validation of Sy...
Software and Systems Engineering Standards: Verification and Validation of Sy...
 
Sachpazis Costas: Geotechnical Engineering: A student's Perspective Introduction
Sachpazis Costas: Geotechnical Engineering: A student's Perspective IntroductionSachpazis Costas: Geotechnical Engineering: A student's Perspective Introduction
Sachpazis Costas: Geotechnical Engineering: A student's Perspective Introduction
 
Arduino_CSE ece ppt for working and principal of arduino.ppt
Arduino_CSE ece ppt for working and principal of arduino.pptArduino_CSE ece ppt for working and principal of arduino.ppt
Arduino_CSE ece ppt for working and principal of arduino.ppt
 
Work Experience-Dalton Park.pptxfvvvvvvv
Work Experience-Dalton Park.pptxfvvvvvvvWork Experience-Dalton Park.pptxfvvvvvvv
Work Experience-Dalton Park.pptxfvvvvvvv
 
Internet of things -Arshdeep Bahga .pptx
Internet of things -Arshdeep Bahga .pptxInternet of things -Arshdeep Bahga .pptx
Internet of things -Arshdeep Bahga .pptx
 
young call girls in Green Park🔝 9953056974 🔝 escort Service
young call girls in Green Park🔝 9953056974 🔝 escort Serviceyoung call girls in Green Park🔝 9953056974 🔝 escort Service
young call girls in Green Park🔝 9953056974 🔝 escort Service
 

Digital logic

  • 1. DIGITAL LOGIC  What is gate?  The Basic Gates  NOT gate  OR gate  AND gate  Universal Logic Gates  NOR gate  NAND gate 1 Presented by, M.Madhu Bala
  • 2. GATES  A digital circuit having one or more input signals but only one output signal is called a gate.  Connecting the basic gates in different ways makes it possible to produce circuits.  Gates are often called logic circuits.  The basic gates can be used to produce any digital system.  The three basic logic circuits are  the inverter (NOT)  the OR gate and  the AND gate 2
  • 3. THE INVERTER (NOT GATE)  A NOT gate has one input signal and one output signal.  The output Y of NOT gate is always complement of input A.  In equation form Y= NOT A Y=A‘ Y=A  There are only two possible voltage levels (low and high) associated with a digital circuit. This fits with the binary number system (0&1)  This is often referred to as two-state operation.  In the positive logic,  the higher voltage level is assigned the binary value 1 (H=1)  the lower voltage level is assigned the binary value 0 .(L=0) 3 A Y=A’ L H H L A Y=A’ 0 1 1 0 Logic Circuit of NOT gate Truth Table
  • 4. THE INVERTER (NOT GATE) TTL NOT Gates Pinout diagram of a 7404 hex inverter  This IC contains six inverters.  After applying +5 V to pin 14 and grounding pin 7, you can connect any or all inverters to other Transistor–Transistor Logic(TTL) devices. 4
  • 5. OR GATE  An OR gate has two or more input signals but only one output signal.  It is called an OR gate because the output voltage is high if any or all of the input voltages are high.  In Boolean equation form Y = A OR B Y = A + B The '+' sign represents the logic operation OR  The number of rows in a truth table equals 2n, where n is the number of inputs 5 Logic Circuit of OR gate A B Y=A+B 0 0 0 0 1 1 1 0 1 1 1 1 Truth Table
  • 6. Three- input OR gate  The inputs are A, B, and C.  When all inputs are low, the output is low.  If any input is high, the output will be high.  Boolean Equation Form: Y = A+B+C 6 OR GATE (CONT..) A B C Y=A+B+C 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1Logic Circuit of 3-input OR gate Truth Table
  • 7. TTL OR Gates This digital IC contains four 2-input OR gates inside a 14- pin DIP. After connecting a supply voltage of +5 V to pin 14 and a ground to pin 7, you can connect one or more of the OR gates to other TTL devices. 7 OR GATE (CONT.)
  • 8. Timing diagram for 2-input OR gate  The input voltages drive pins 1 and 2 of a 7432.  The output (pin 3) is low only when both inputs are low.  The output is high the rest of the time. 8 OR GATE (CONT..)
  • 9.  The AND gate has a high output only when all inputs are high. otherwise the output will be low.  AND gate also known as all-or-nothing gate.  In Boolean equation form Y =A AND B Y=A.B Y=AB The '.' sign represents the logic AND operation. 9 AND GATE A B Y=AB 0 0 0 0 1 0 1 0 0 1 1 1Logic Circuit of AND gate Truth Table
  • 10. Three- input AND gate  The inputs are A, B, and C.  When all inputs are high, the output is high.  If even one input is low, the output is in the low state.  In Boolean equation form: Y=A.B.C Y=ABC 10 AND GATE (CONT..) A B C Y=ABC 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 Logic Circuit of AND gate Truth Table
  • 11. TTL AND Gates  This digital IC contains four 2-input AND gates.  After connecting a supply voltage of +5V to pin 14 and a ground to pin 7, you can connect one or more of the AND gates to other TTL devices.  TTL AND gates are also available in triple 3-input and dual 4-input packages. 11 AND GATE (CONT..)
  • 12. Timing diagram for a 2-input AND gate The input voltages drive pins 1 and 2 of a 7408. the output (pin 3) is high only when both inputs are high. The output is low the rest of the time. 12 AND GATE (CONT..)
  • 13. The NAND & NOR gates are called universal gates because they can perform all the logical operations of basis gates like AND, OR, NOT. 13 Universal Logic Gate
  • 14.  The circuit of NOR gate is a circuit of OR gate followed by an inverter  The output of NOR gate is Y=A+B  NOR Gates also called a NOT-OR gate.  All inputs must be low to get a high output.  If any input is high, the output is low. 14 NOR GATE Logic Circuit of NOR Gates Abbreviated form Standard form IEEE form Truth Table A B Y=(A+B)’ 0 0 1 0 1 0 1 0 0 1 1 0
  • 15. Pin- out Diagram of NOR gate 15 NOR GATE (CONT.)
  • 16. Bubbled AND Gate  Bubbled AND Gate inverters on the input lines of an AND gate.  The output of bubbled AND gate and NOR gate are identical.  Therefore, these two circuits are equivalent and thus interchangeable.  The output of bubbled AND gate is represented as Y= A . B 16 NOR GATE (CONT.) Abbreviated form Standard form Truth Table A B A’ B’ Y=A’.B’ 0 0 1 1 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 Logic Circuit of Bubbled AND Gates
  • 17. De Morgan's First Theorem NOR gate : Y=(A+B)’ bubbled AND gate : Y=A’B’  The outputs are equal for the same inputs, so that (A+B)’ = A’B’  The complement of a sum equals the product of the complements. This identity is known as De Morgan’s, first theorem.  This can also be proved by comparing the truth tables of NOR and bubbled AND gates.  Three input NOR gate and three input bubbled AND gate are identical and it can write, (A+ B + C)' = A'B'C'  This equivalence can be extended to gates or circuits for larger number of inputs, too. 17 NOR GATE (CONT.)
  • 18. NOT from NOR  To get a NOT gate, tie inputs of NOR gate together so that there is only one input to the circuit.  If input is 0, then both the inputs to NOR gate are 0 that gives output 1.  Similarly, if input is 1, both the inputs to NOR gate are 1 that gives output 0.  Therefore the output of circuit is complement of its input and thus gives NOT operation. 18 NOR GATE (CONT.)
  • 19. OR from NOR  To get a OR gate, two NOR gates are used.  The first NOR gate performs usual NOR operation.  The second NOR gate performs as NOT gate and inverts the NOR logic to OR 19 NOR GATE (CONT.) A+B
  • 20. AND from NOR  To get a AND gate, three NOR gates are used.  The first and second NOR gate performs as NOT gate.  NOT gates are replaced by NOR equivalent. Since NOR gate is NOT operation followed by OR we invert the  output of example 2.3, shown in Fig. 2.9b to get output of this circuit. Thus output of circuit in Fig. 2.2 lc is  high only when both the inputs are high and it functions like an AND gate. 20 NOR GATE (CONT.)
  • 21.  The circuit of NAND gate is a circuit of AND gate followed by an inverter  The output of NAND gate is Y=AB "Y equals NOT A AND B"  NAND Gates also called a NOT-AND gate.  All inputs must be high to get a low output.  If any input is low, the output is high. 21 NAND GATE Logic Circuit of NAND Gate Abbreviated form Standard form IEEE form Truth Table A B AB Y=AB 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0
  • 22. Pin- out Diagram of NAND gate 22 NAND GATE (CONT.)
  • 23. Bubbled OR Gate  Bubbled OR Gate inverters on the input lines of an OR gate.  The output of bubbled OR gate and NAND gate are identical.  Therefore, these two circuits are equivalent and thus interchangeable.  The output of bubbled OR gate is represented as Y=A+B 23 NAND GATE (CONT.) A B A B Y=A+B 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 1 0 0 0 Abbreviated form Standard form Truth TableLogic Circuit of Bubbled OR Gate
  • 24. De Morgan's Second Theorem NAND Gate :(AB)’ Bubbled OR Gate : Y=A’+B’  The outputs are equal for the same inputs, so that (AB)’ = A’+B’  The complement of a product equals the sum of the complements. This identity is known as De Morgan’s second theorem.  This can also be proved by comparing the truth tables of NAND gate and bubbled OR gate.  Three input NAND gate and three input bubbled OR gate are identical and it can write, (ABC)' = A’+B‘+C’  This equivalence can be extended to gates or circuits with any number of inputs. 24 NAND GATE (CONT.)