Chapter 06 Combinational Logic Functions

Chapter 6
Combinational Logic
Functions

2
Basic Decoder
• Decoder: A digital circuit designed to detect
the presence of a particular digital state.
• Can have one output or multiple outputs.
• Example: 2-Input NAND Gate detects the
presence of ‘11’ on the inputs to generate a
‘0’ output.

3
Single-Gate Examples
• If the inputs to a 4-Input NAND are
given as , then the NAND
detects the code 0001. The output is a 0
when the code 0001 is detected.
• This type of decoder is used in Address
Decoding for a PC System Board.
4321 , DD,D,D

4
Multiple Output Decoders
• Decoder circuit with n inputs can
activate m = 2n load circuits.
• Called a n-line-to-m-line decoder, such
as a 2-to-4 or a 3-to-8 decoder.
• Usually has an active low enable
that enables the decoder outputs.
G

5
Truth Table for a 3-to-8 Decoder
111110110100
111111011000
111111100000
11111111XXX1
YYYYYYYYDDDG 76543210012


6
Truth Table for a 3-to-8 Decoder

7
Simulation
• Simulation: The verification of a digital
design using a timing diagram before
programming the design in a CPLD.
• Used to check the Output Response of
a design to an Input Stimulus using a
timing diagram.

9
VHDL Binary Decoder
• Use select signal assignment
statements constructs or conditional
signal assignment statements
constructs.

10
2-to-4 Decoder VHDL Entity
• Using a select signal assignment statement:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY decode3 IS
PORT(
d : IN STD_LOGIC_VECTOR (1 downto 0);
y : OUT STD_LOGIC_VECTOR (3 downto 0));
END decode3;

11
Selected Signal Entity
• In the previous slide, the Entity used a
STD LOGIC Array for Inputs and
Outputs.
• The Y : OUT STD_LOGIC_VECTOR(3
downto 0) is equal to Y3, Y2, Y1, Y0.
• The STD_LOGIC Data Type is similar to
BIT but has added state values such as
Z, X, H, and L instead of just 0 and 1.

12
Selected Signal Assignments
• Uses a VHDL Architecture construct
called WITH SELECT.
• Format is:
– WITH (signal input(s)) SELECT.
– Signal input states are used to define the
output state changes.

13
2-to-4 Decoder VHDL Architecture
ARCHITECTURE decoder OF decode3 IS
BEGIN
WITH d SELECT
y <= “0001” WHEN “00”,
“0010 WHEN “01”,
“0100” WHEN “10”,
“1000” WHEN “11”,
“0000” WHEN others;
END decoder;

14
Decoder Architecture
• The decoder Architecture used a
SELECT to evaluate d to determine the
Output y.
• Both d and y are defined as an Array
(or bus or vector) Data Type.
• The last state for WHEN OTHERS is
added for the other logic states (Z, X, H,
L, etc.).

15
Seven-Segment Displays
• Seven-Segment Display: An array of
seven independently controlled LEDs
shaped like an 8 that can be used to
display decimal digits.

18
Common Anode Display
• Common Anode Display (CA): A seven-
segment display where the anodes of all
the LEDs are connected together to VCC
and a ‘0’ turns on a segment (a to g).

19
Common Cathode Display
• Common Cathode Display (CC): A
seven-segment display where all the
cathodes are connected and tied to
ground, and a ‘1’ turns on a segment.

22
Seven-Segment Decoder/Driver – 1
• Receives a BCD (Binary Coded
Decimal) 4-Bit input, outputs a BCD
digit 0000 – 1001 (0 through 9).
• Generates Outputs (a–g) for each of the
display LEDs.
• Requires a current limit series resistor
for each segment.

23
Seven-Segment Decoder/Driver – 2
• Decoders for a CC-SS have active high
outputs while decoders for a CA-SS have
active low outputs (a to g).
• The outputs generated for the binary input
combinations of 1010 to 1111 are “don’t
cares”.
• The decoder can be designed with VHDL or
MSI Logic (7447, 7448).

24
Digit D3 D2 D1 D0 a b c d e f g
0 0 0 0 0 0 0 0 0 0 0 1
1 0 0 0 1 1 0 0 1 1 1 1
2 0 0 1 0 0 0 1 0 0 1 0
3 0 0 1 1 0 0 0 0 1 1 0
4 0 1 0 0 1 0 0 1 1 0 0
5 0 1 0 1 0 1 0 0 1 0 0
6 0 1 1 0 1 1 0 0 0 0 0
7 0 1 1 1 0 0 0 1 1 1 1
8 1 0 0 0 0 0 0 0 0 0 0
9 1 0 0 1 0 0 0 1 1 0 0
SS Decoder/Driver Truth Table

25
SS Decoder/Driver Truth Table

26
Decoder/Driver Entity (CA)
ENTITY bcd_7seg IS
PORT(
d3, d2, d1, d0 : IN BIT;
a, b, c, d, e, f, g : OUT BIT;
END bcd_7seg;

27
Decoder/Driver Architecture – 1
ARCHITECTURE seven_segment OF bcd_7seg IS
SIGNAL input : BIT_VECTOR (3 downto 0);
SIGNAL output : BIT_VECTOR (6 downto 0);
BEGIN
input <= d3 & d2 & d1 & d0;
-- Uses two intermediate signals called input and output (internal
no pins)
-- Creates an array by using the concatenate operator (&)
In this case input(3) <= d3, input(2) <= d2, etc.

28
WITH input SELECT
output <= “0000001” WHEN “0000”,
“1001111” WHEN “0001”,
“0010010” WHEN “0010”,
“0000110“ WHEN “0011”,
• • •
• • •
• • •

29
a <= output(6);
b <= output(5);
c <= output(4);
d <= output(3);
e <= output(2);
f <= output(1);
g <= output(0);
END seven_segment

30
SS VHDL File Description
• In the preceding example file, a
concurrent select signal assignment
was used (WITH (signals) SELECT.
• The intermediate output signals were
mapped to the segments (a to g).
• Example: when Input (D3 – D0) is 0001,
the decoder sets a=d=e=f=g=1, b=c=0.

31
Sequential Process in VHDL
• A VHDL Process is a construct that
encloses sequential statements that are
executed when a signal in a sensitivity
list changes.

32
Sequential Process Basic Format
• Basic Format:
PROCESS(Sensitivity List)
BEGIN
Sequential Statements;
END PROCESS;

Multiplexer
• library ieee;
• use ieee.std_logic_1164.all;
• entity multiplexers_1 is
• port (A, B, C, D : in std_logic;
• S : in std_logic_vector (1 downto 0);
• O : out std_logic);
• end multiplexers_1;
• architecture archi of multiplexers_1 is
• begin
• process (A, B, C, D, S)
• begin
• case s is
• when "00" => O <= A;
• when "01" => O <= B;
• when "10" => O <= C;
• when "11" => O <= D;
• when others => O <= A;
• end case;
• end process;
• end archi;

34
IF THEN ELSE
• The IF THEN ELSE Statements were
used for conditional testing of some
inputs.
• IF the data is this value THEN do these
statements ELSE do this.
• This is a very simple statement that is
used a great deal in sequential logic.

35
Encoders
• Encoder: A digital circuit that generates
a specific code at its outputs in
response to one or more active inputs.
• It is complementary in function to a
decoder.
• Output codes are usually Binary or
BCD.

36
Priority Encoders
• Priority Encoder: An encoder that
generates a code based on the highest-
priority input.
• For example, if input D3 = input D5, then
the output is 101, not 011. D5 has a
higher priority than D3 and the output
will respond accordingly.

37
8-to-3 Encoder Truth Table
11100000001
00100001000
11000010000
01000100000
10001000000
0000000000
Q0Q1Q2D0D1D2D3D4D5D6D7
InputsHighActive

1

38
Priority Encoder Equations
DDDDDDDDDDQ
DDDDDDDDQ
DDDDQ
12463465670
245345671
45672




39
Priority Encoder VHDL Entity
-- hi_pri8a.vhd
ENTITY hi_pri8a IS
PORT(
d : IN BIT_VECTOR (7 downto 0);
q : OUT BIT_VECTOR (2 downto 0));
END hi_pri8a;

40
Priority Encoder VHDL Architecture
ARCHITECTURE a OF hi_pri8a IS
BEGIN
-- Concurrent Signal Assignments
q(2) <= d(7) or d(6) or d(5) or d(4);
q(1) <= d(7) or d(6)
or ((not d(5)) and (not d(4)) and d(3))
or ((not d(5)) and (not d(4)) and d(2));
q(0) <= -- in a similar fashion
END a;

41
Another VHDL Encoder – 1
-- hi_pri8b.vhd
ENTITY hi_pri8a IS
PORT(
d : IN BIT_VECTOR (7 downto 0);
q : OUT INTEGER RANGE(0 TO 7);
END hi_pri8b;

42
Another VHDL Encoder – 2
ARCHITECTURE a OF hi_pri8b IS
BEGIN
--encoder;
q <= 7 WHEN d(7) = ‘1’ ELSE
6 WHEN d(6) = ‘1’ ELSE
0;
END a;

43
Basic Multiplexers (MUX)
• (MUX): A digital circuit that directs one of
several inputs to a single output based on the
state of several select inputs.
• A MUX is called a m-to-1 MUX.
• A MUX with n select inputs will require m = 2n
data inputs (e.g., a 4-to-1 MUX requires 2
select inputs S1 and S0).

46
4-to-1 Multiplexers Truth Table
S1 S0 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

47
Multiplexer Logic
• Boolean expression for a 4-to-1 MUX is
• This expression can be expanded to
any size MUX so the VHDL architecture
could use a very long concurrent
Boolean statement.
013012011010 SSDSSDSSDSSDY 

48
Double Subscript Notation
• Naming convention in which variables are
bundled in numerically related groups, the
elements of which are themselves numbered.
• The first subscript identifies the group that a
variable belongs to (D01, D00).
• The second subscript indicates which
element of the group a variable represents.

49
Truth Table for a 4-to-1
4-bit Bus MUX
S1 S0 Y3 Y2 Y1 Y0
0 0 D03 D02 D01 D00
0 1 D13 D12 D11 D10
1 0 D23 D22 D21 D20
1 1 D33 D32 D31 D30

50
Truth Table for a 4-to-1
4-bit Bus MUX

51
VHDL Constructs For MUXs
• The following three VHDL constructs
can be used to describe the Multiplexer:
– Concurrent Signal Assignment Statement
– Select Signal Assignment Statement
– CASE Statement

52
PROCESS and Sensitivity List
• PROCESS: A VHDL construct that
contains statements that are executed if
a signal in its sensitivity list changes.
• Sensitivity list: A list of signals in a
PROCESS statement that are
monitored to determine whether the
Process should be executed.

53
Case Statement
• A case statement is a VHDL construct
in which there is a choice of statements
to be executed, depending on the value
of a signal or variable.

54
Case VHDL Template
CASE __expression IS
WHEN __constant_value =>
__statement;
__statement;
WHEN __constant_value =>
__statement;
__statement;
WHEN OTHERS =>
__statement;
__statement;
END CASE;

55
MUX 4-to-1 VHDL – 1
• Basic Entity declaration for a 4-to-1 MUX:
ENTITY mux4case IS
PORT(
d0, d1, d2, d3 : IN BIT;
s : IN BIT_VECTOR (1 downto 0);
y : OUT BIT);
END mux4case;

56
ARCHITECTURE mux4to1 OF mux4case IS
BEGIN
-- Monitor select inputs and execute if they change
PROCESS(s)
BEGIN
CASE s IS

57
WHEN "00" => y <= d0;
WHEN "01" => y <= d1;
WHEN "10" => y <= d2;
WHEN "11" => y <= d3;
WHEN others => y <= '0';
END CASE;
END PROCESS;
END mux4to1;

58
Multiplexer Applications
• Used in directing multiple data sources
to a single processing element such as
multiple CD Player Streams to a DSP.
• Used in Time Division Multiplexing
(TDM) by the Phone Service to
multiplex multiple voice channels on a
single coax line (or fiber).

59
Demultiplexer Basics – 1
• Demultiplexer: A digital circuit that
uses a decoder to direct a single input
(from a MUX) to one of several outputs.
• A DEMUX performs the reverse
operation of a MUX.
• The selected output is chosen by the
Select Inputs (as in a MUX).

60
Demultiplexer Basics – 2
• Designated as a 1-to-n DEMUX that requires
m select inputs such that n outputs = 2m
select inputs.
• 1-to-4 DEMUX Equations:
• They are similar to a MUX and can be
designed using CASE Statements.
.SSDYSSDY
SSDYSSDY
)()(
)()(
01030102
01010100
;
;;



64
Demultiplexer VHDL Entity
ENTITY dmux8 IS
PORT(
s : IN STD_LOGIC_VECTOR (2 downto 0);
d : IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR (0 to 7));
END dmux8;

65
Demultiplexer VHDL Architecture
ARCHITECTURE a OF dmux8 IS
SIGNAL inputs : STD_LOGIC_VECTOR (3 downto 0);
BEGIN
inputs <= d & s;
WITH inputs select
Y <= “01111111” WHEN “0000”,
“10111111” WHEN “0001”,
• • •
• • •
END a;

66
Demultiplexer VHDL Architecture

67
Parity Basics – 1
• Parity: A digital system that checks for errors
in a n-Bit Binary Number or Code.
• Even Parity: A parity system that requires the
binary number and the parity bit to have an
even # of 1s.
• Odd Parity: A parity system that requires the
binary number and the parity bit to have an
Odd # of 1s.

68
Parity Basics – 2
• Parity Bit: A bit appended on the end of
a binary number or code to make the #
of 1s odd or even depending on the
type of parity in the system.
• Parity is used in transmitting and
receiving data by devices in a PC called
UARTs, that are on the COM Port.

70
Parity Calculation
• N1 = 0110110:
– It has four 1s (an even number).
– If Parity is ODD, the Parity Bit = 1 to make it an
odd number (5).
– If Parity is EVEN, the Parity Bit = 0 to keep it an
even number (4).
• N2 = 1000000:
– One 1 in the data.
– Podd = 0.
– Peven = 1.

71
Parity Generation HW – 1
• A basic two-bit parity generator can be
constructed from a XOR Gate.
• When the two inputs are 01 or 10, the
output is a 1 (so this is even parity).
• When the two inputs are 00 or 11, the
output is a 0.
• For a parity generator of n bits, add
more gates.

72
Parity Generator HW – 2
• Cascading a long chain of XOR gates
could cause excessive propagation
delays.
• To check for a Parity error, the receiver
(RX) just generates a new Parity Bit (P1)
based on the received parallel data and
then compares it to the parity bit
transmitted (P2).

73
Parity Generator HW – 3
• If there is an error, the two bits (P1 and P2)
will not be equal, and we can use a two-bit
magnitude comparator to check this (an XOR
gate).
• This check is called syndrome.
– If there are no errors, the syndrome output (Perr) is
0.
• Parity is not a foolproof system.
– If two bits are in error, the error is not detected.

75
VHDL GENERATE Statement
__generate_label:
FOR __index_variable IN __range GENERATE
__statement;
__statement;
END GENERATE;

76
4-Bit Parity VHDL Code – 1
LIBRARY ieee;
USE ieee.std_logic1164.ALL;
ENTITY parity4_gen IS
PORT(
d : IN STD_LOGIC_VECTOR (0 to 3);
pe ; OUT STD_LOGIC);
END parity4_gen;

77
4-Bit Parity VHDL Code – 2
ARCHITECTURE parity OF parity4_gen IS
SIGNAL p : STD_LOGIC_VECTOR (1 to 3);
BEGIN
p(1) <= d(0) xor d(1);
parity_generate:
FOR i IN 2 to 3 GENERATE
p(i) <= p(i-1) xor d(i);
END GENERATE;
pe <= p(3);
END parity;

Chapter 06 Combinational Logic Functions

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