Digital Design with CPLD Applications and VHDL

1. Chapter 3
Boolean Algebra and
Combinational Logic

2. 2
Logic Gate Network
• Two or more logic gates connected
together.
• Described by truth table, logic
diagram, or Boolean expression.

3. 3
Logic Gate Network
Y=AB + C
Let’s derive the truth table for this network

4. 4
Boolean Expression for Logic
Gate Network
• Similar to finding the expression for a
single gate.
• Inputs may be compound expressions
that represent outputs from previous
gates.

5. 5
Boolean Expression for Logic
Gate Network
= +
Here, we just
work our way
through from
left to right and
write out the
intermediate
terms...

6. 6
Bubble-to-Bubble Convention
• Choose gate symbols so that outputs
with bubbles connect to inputs with
bubbles. (If it’s practical…)
• Results in a cleaner notation and a
clearer idea of the circuit function.

7. 7
Bubble-to-Bubble Convention
= + +
+
Here, we’ve just used
DeMorgan’s Equivalent
cct
For the bottom gate…

8. 8
Let’s redraw this removing as many bubble to bubble
connections then see how much easier it is to derive the
Boolean expression for S
Example 3.3
Figure 3.5 b

9. 9
Order of Precedence
• Unless otherwise specified, in Boolean
expressions AND functions are
performed first, followed by ORs.
• To change the order of precedence, use
parentheses.

10. 10
Order of Precedence
+
+
++
+
++

11. 11
Simplification by Double
Inversion
• When two bubbles touch, they cancel
out.
• In Boolean expressions, bars of the
same length cancel.

12. 12
Logic Diagrams from Boolean
Expressions
• Use order of precedence.
• A bar over a group of variables is the
same as having those variables in
parentheses.

13. 13
Logic Diagrams from Boolean
Expressions
+ +=
Do the
AND’s first,
then the OR
+ +=

14. 14
Truth Tables from Logic Diagrams
or Boolean Expressions
• Two methods:
– Combine individual truth tables from each
gate into a final output truth table.
– Develop a Boolean expression and use it
to fill in the truth table.

15. 15
Truth Tables from Logic Diagrams
or Boolean Expressions
+

16. 16
Truth Tables from Logic Diagrams
or Boolean Expressions
So here we’ve just
combined the T/T columns
from the individual gates in
the diagram

17. 17
Circuit Description Using Boolean
Expressions
• Product term:
– Part of a Boolean expression where one or
more true or complement variables are
ANDed.
• Sum term:
– Part of a Boolean expression where one or
more true or complement variables are
ORed.

18. 18
Circuit Description Using Boolean
Expressions
• Sum-of-products (SOP):
– A Boolean expression where several
product terms are summed (ORed)
together.
• Product-of-sum (POS):
– A Boolean expression where several sum
terms are multiplied (ANDed) together.

19. 19
Examples of SOP and POS
Expressions
)()()(:POS
:SOP
CACBBAY
DACBABY



20. 20
SOP and POS Utility
• SOP and POS formats are used to
present a summary of the circuit
operation.

21. 21
Bus Form
• A schematic convention in which each
variable is available, in true or
complement form, at any point along a
conductor.

22. 22
Bus Form

23. 23
Deriving a SOP Expression from
a Truth Table
• Each line of the truth table with a 1 (HIGH) output
represents a product term .
• Each product term is summed (ORed).
• Minterm = Boolean product term that contains
EACH variable ONCE in true or complemented form
• Maxterm = Boolean sum term that contains EACH
variable ONCE in true or complemented form
From T/T
To gates…

24. 24
The Big Picture
A significant goal of this class is synthesis
How do we get from a specification to hardware?
T/T → minterms → Boolean expression →
synthesis → gates
Do Fig 3.16, generate SOP from T/T then gates…
•Pg16r2

25. 25
Digital
Circuit
A
B
C
Y
Figure 3.16 Digital Circuit with Unknown Function
A B C Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
First, find the minterms and the
SOP solution
Then lets find the maxterms and
the POS solution.

26. 26
Here is the SOP
implementation

27. 27
Now – the other way - Deriving a POS
Expression from a Truth Table
• Each line of the truth table with a 0 (LOW)
output represents a sum term.
• The sum terms are multiplied (ANDed).
• Let’s revisit the last example – this time do
the Product of Sums solution…
– Generate the maxterms then OR inputs together
– then AND to get the final output function

28. 28
Deriving a POS Expression from
a Truth Table
This is kind of a worst
case T/T – eight
terms for either SOP
or POS
This would require
eight – 4 input AND’s
and one 8 input OR…

29. 29
Theorems of Boolean Algebra
• Used to minimize a Boolean expression
to reduce the number of logic gates in a
network.
• 24 theorems.

30. 30
Commutative Property
• The operation can be applied in any
order with no effect on the result.
– Theorem 1: xy = yx
– Theorem 2: x + y = y + x
lets do the truth table on
the board...

31. 31
Associative Property
• The operands can be grouped in any
order with no effect on the result.
– Theorem 3: (xy)z = x(yz) = (xz)y
– Theorem 4: (x + y) + z = x + (y + z) = (x + z) + y

32. 32
Distributive Property
• Allows distribution (multiplying through)
of AND across several OR functions.
• Theorem 5: x(y + z) = xy + xz
• Theorem 6: (x + y)(w + z) = xw + xz + yw + yz
– Theorem 6 effectively changes a POS representation to SOP
Let’s do theorem 5 on the board…
Also do example 3.9 from the text…

33. 33
Distributive Property
SOPPOS

34. 34
Operations with Logic 0
• Theorem 7: x  0 = 0
• Theorem 8: x + 0 = x
• Theorem 9: x  0 = x
Let’s do theorem 7 on the board…

35. 35
Operations with Logic 1
• Theorem 10: x  1 = x
• Theorem 11: x + 1 = 1
• xx 1:12Theorem 
These mostly make sense, but lets check theorem
12…

36. 36
Operations with Logic 0 and Logic 1

37. 37
Operations with the Same
Variable
• Theorem 13: x  x = x
• Theorem 14: x + x = x
• Theorem 15: x  x = 0

38. 38
Operations with the Complement
of a Variable
•
•
• 1:18Theorem
1:17Theorem
0:16Theorem



xx
xx
xx
L6

39. 39
Operations with True or
Complement of a Variable

40. 40
Double Inversion
• xx:19Theorem 

41. 41
DeMorgan’s Theorem
•
• yxyx
yxyx
:21Theorem
:20Theorem


Lets do these on the board…

42. 42
Multivariable Theorems
• Theorem 22: x + xy = x
• Theorem 23: (x + y)(x + z) = x + yz
• yxyxx:24Theorem 
Let’s check these on the board…

43. 43
Multivariable Theorems
Do Ex 3.13 from notes Pg 21r2
Do review questions 3.3 from notes Pg21r2

44. 44
Simplifying SOP and POS
Expressions
• A Boolean expression can be simplified
by:
– Applying the Boolean Theorems to the
expression
– Application of graphical tool called a
Karnaugh map (K-map) to the expression

45. 45
Simplifying an Expression
BAY
xx
BAY
x
CBAY
BA
CBABAY
)1(:10theoremapplying
1
1)(1:11theoremapplying
)(1
termcommontheoutfactoring






Let’s do a few more on the board…

46. 46
Simplifying an Expression
ABY
DCCDABY
AB
ABDCABCDABY
BADCBACDABY




so1,toresolvestermlastThe
outFactor
20theoremsDeMorgan'applying
)1)((
)(
))((

47. 47
Simplification By Karnaugh
Mapping
• A Karnaugh map, called a K-map, is a
graphical tool used for simplifying
Boolean expressions.
• Makes use of humans ‘pattern
recognition’ skills
• K-map works well for 2,3,4 variables,
more difficult for 5 or 6…

48. 48
Construction of a Karnaugh Map
• Square or rectangle divided into cells.
• Each cell represents a line in the truth
table.
• Cell contents are the value of the
output variable on that line of the
truth table.

49. 49
Construction of a Karnaugh Map

50. 50
Construction of a Karnaugh Map

51. 51
Construction of a Karnaugh Map
Let’s draw the truth
table for this on the
board to see how the
K-map is loaded…

52. 52
K-map Cell Coordinates
• Adjacent cells differ by only one
variable.
• Grouping adjacent cells allows
canceling variables in their true and
complement forms.

53. 53
Grouping Cells
• Cells can be grouped as pairs, quads,
and octets.
• A pair cancels one variable.
• A quad cancels two variables.
• An octet cancels three variables.

54. 54
Grouping Cells
AY 

55. 55
Grouping Cells
CY 

56. 56
Grouping Cells
BY 

57. 57
Grouping Cells along the Outside
Edge
• The cells along an outside edge are
adjacent to cells along the opposite
edge.
• In a four-variable map, the four corner
cells are adjacent.

58. 58
Grouping Cells along the Outside
Edge

59. 59
Loading a K-Map from a Truth
Table
• Each cell of the K-map represents one
line from the truth table.
• The K-map is not laid out in the same
order as the truth table.

60. 60
Loading a K-Map from a Truth
Table

61. 61
Loading a K-Map from a Truth
Table

62. 62
Multiple Groups
• Each group is a term in the maximum
SOP expression.
• A cell may be grouped more than once
as long as every group has at least one
cell that does not belong to any other
group. Otherwise, redundant terms will
result.

63. 63
Multiple Groups

64. 64
Maximum Simplification
• Achieved if the circled group of cells on
the K-map are as large as possible.
• There are as few groups as possible.

65. 65
Maximum
Simplification
• Max group
size
• Min number
of groups

66. 66
Using K-Maps for Partially
Simplified Circuits
• Fill in the K-map from the existing
product terms.
• Each product term that is not a minterm
will represent more than one cell.
• Once completed, regroup the K-map for
maximum simplification.

67. 67
Using K-Maps for Partially
Simplified Circuits

68. 68
Using K-Maps for Partially
Simplified Circuits

69. 69
Don’t Care States
• The output state of a circuit for a
combination of inputs that will never
occur.
• Shown in a K-map as an “x”.

70. 70
Value of Don’t Care States
• In a K-map, set “x” to a 0 or a 1,
depending on which case will yield the
maximum simplification.

71. 71
Value of Don’t Care States

72. 72
POS Simplification Using
Karnaugh Mapping
• Group those cells with values of 0.
• Use the complements of the cell
coordinates as the sum term.

73. 73
POS Simplification Using
Karnaugh Mapping
Let’s do an example next…

74. 74
Simplification by DeMorgan’s Equivalent Gates
Bubble-to-Bubble Convention – Step 1
• Start at the output and work towards the
input.
• Select the OR gate as the last gate for an
SOP solution.
• Select the AND gate as the last gate for an
POS solution.

75. 75
Simplification by DeMorgan’s Equivalent Gates
Bubble-to-Bubble Convention – Step 2
• Choose the active level of the output if
necessary.
• Go back to the circuits inputs to the next level
of gating.

76. 76
Simplification by DeMorgan’s Equivalent Gates
Bubble-to-Bubble Convention – Step 3
• Match the output of these gates to the input of
the final gate. This may require converting the
gate to its DeMorgan’s equivalent.
• Repeat Step 2 until you reach the circuits
input

77. 77
Simplification by DeMorgan’s Equivalent Gates
Bubble-to-Bubble Convention
=
See Pg 120 of the text, there is an error in Fig 3.63
L7

78. 78
Simplification by DeMorgan’s Equivalent Gates
Bubble-to-Bubble Convention
=
=
So here by using the DeMorgan’s equivalent circuit we
are able to remove the bubble to bubble connection

79. 79
Universality of NAND/NOR Gates
• Any logic gate can be implemented
using only NAND or only NOR gates.

80. 80
NOT from NAND
• An inverter can be constructed from a
single NAND gate by connecting both
inputs together.

81. 81
NOT from NAND

82. 82
AND from NAND
• The AND gate is created by inverting
the output of the NAND gate.
BABAY 

83. 83
AND from NAND

84. 84
OR and NOR from NAND
YXYX
YXYX
NOR
OR



85. 85
OR from NAND

86. 86
NOR from NAND

87. 87
NOT from NOR
• An inverter can be constructed from a
single NOR gate by connecting both
inputs together.

88. 88
NOT from NOR

89. 89
OR from NOR
• The OR gate is created by inverting
the output of the NOR gate.
BABAY 

90. 90
OR from NOR

91. 91
AND and NAND from NOR
YXYX
YXYX
NAND
AND



92. 92
AND from NOR

93. 93
NAND from NOR
Note error on Pg 124 of the text
should be
Recall:
XY
YX
XY ¹ XY

94. 94
Practical Circuit Implementation
in SSI
• Not all gates are available in TTL.
• TTL components are becoming more
difficult to find.
• In a circuit design, it may be necessary
to replace gates with other types of
gates in order to achieve the final
design.

95. Practical Implementation of Small Scale Integration Devices
• So far, we have focused
on simplification of
designs to save time,
space, gates, power, etc.
• Now, let’s examine some
practical information
related to devices you will
use in the lab
Most device available in several physical
Packages e.g. DIP, Small Outline IC etc.
Gate packages generally have 1,2,3,4 or
6 gates in a pkg – limited nbr of pins! 95

96. A few important design notes
• All devices, regardless of the physical package require
Vcc and Gnd
• Un-used devices need to be pulled Hi or Lo to prevent
noise or oscillation
• Unused TTL – configure for o/p = HIGH
• Unused CMOS – Hi or Lo – either is OK
• Every circuit requires a schematic and / or block
diagram with pin numbers, Vcc and Gnd labeled etc. –
this really speeds up troubleshooting
96

97. Pin
accurate
schematic,
with unused
gates
optimally
configured.
Note Vcc
and Gnd.
97
74LS04 Hex inverter
74LS11 Quad 3 i/p AND
74LS32 Quad 2 i/p OR
Build your own three input OR Gate

98. • Don’t mix logic families (if you have a choice)
• Don’t connect outputs together
– Outputs go to inputs (unless tristate…)
• Ensure every package has Vcc and ground
• Configure unused gates
• Let’s do example 3.27
98
More on Design

99. Here is the authors solution –
he has used DME to create a
four i/p OR with
Inverting inputs – perhaps a
bit messy.
Another way would be to
make a 4 i/p OR from
3 – two i/p OR gates.
His result is pin accurate, but
has quite a bit of negative
logic – this makes
troubleshooting more difficult
99

100. More on Positive Logic
• Easier for others to understand
• Permits faster integration into larger
projects
• In industry, the cost related to
troubleshooting, integration, regression
testing and documentation swamp the
cost of a few extra gates on the pcb
100

101. 101
Pulsed Operation
• The enabling and inhibiting properties of the
basic gates are used to pass or block
pulsed digital signals.
• The pulsed signal is applied to one input.
• One input is used to control (enable/inhibit)
the pulsed digital signal.

102. 102
Pulsed Operation
Reset

103. 103
Pulsed Operation

104. 104
General Approach to Logic
Circuit Design – 1
• Have an accurate description of the
problem.
• Understand the effects of all inputs on
all outputs.
• Make sure all combinations have been
accounted for.

105. 105
General Approach to Logic
Circuit Design – 2
• Active levels as well as the
constraints on all inputs and outputs
should be specified.
• Each output of the circuit should be
described either verbally or with a
truth table.

106. 106
General Approach to Logic
Circuit Design – 3
• Look for keywords AND, OR, NOT that can
be translated into a Boolean expression.
• Use Boolean algebra or K-maps to simplify
expressions or truth tables.
• Generate gate schematics from simplified
expressions or truth tables
Lets do Example 3.29